Iterative solution of ODE-PDE-AE systems for RF circuit simulation. - Omar Wing; Tan Jun; Jinmei Lai; Junyan Ren; Qianling Zhang (ISCAS (4), 2002)

Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulation. - Xinyu Wu; Zaiman Chen; Jinmei Lai 001; Qianling Zhang; Omar Wing; Junyan Ren (ASP-DAC, 2003)

An implementation of a CMOS down-conversion mixer for GSM1900 receiver. - Fangqing Chu; Wei Li 038; Junyan Ren (ASP-DAC, 2006)

A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet. - Lu Ping; Ye Fan 001; Junyan Ren (ISCAS, 2006)

Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System. - Liang Liu 002; Junyan Ren; Xuejing Wang; Fan Ye 001 (ISCAS, 2007)

A High-Speed High-Resolution Low-Distortion CMOS Bootstrapped Switch. - Lei Wang; Junyan Ren; Wenjing Yin; Tingqian Chen; Jun Xu 011 (ISCAS, 2007)

Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication System. - Zhuo Xu; Junyan Ren; Xuejing Wang; Fan Ye 001 (ISCAS, 2007)

A Power-Optimized CMOS Quadrature VCO with Wide-Tuning Range for UWB Receivers. - Zhujin Zhou; Ning Li 007; Wei Li 038; Junyan Ren (ISCAS, 2007)

A Novel Synchronizer for OFDM-based UWB System on New Preamble Design. - Xuejing Wang; Liang Liu 002; Fan Ye 001; Junyan Ren; Bo Hu (PIMRC, 2007)

Design of Highly-Parallel, 2.2Gbps Throughput Signal Detector for MIMO Systems. - Liang Liu 002; Xiaojing Ma 001; Fan Ye 001; Junyan Ren (ICC, 2008)

A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend. - Lei Luo; Kaihui Lin; Long Cheng; Liren Zhou; Fan Ye 001; Junyan Ren (ESSCIRC, 2009)

A Novel Operational Amplifier for Low-voltage Low-power SC Circuits. - Mingjun Fan; Junyan Ren; Yao Guo; Yuanwen Li; Fan Ye 001; Ning Li 007 (ISCAS, 2009)

A Low Power Low Voltage 16 Bit Audio SigmaDelta Modulator. - Xi Gou; Yiran Li; Jian-qiu Chen; Jun Xu 011; Junyan Ren (ISCAS, 2009)

A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator. - Ping Lu; Danfeng Chen; Fan Ye 001; Junyan Ren (SoCC, 2009)

QuickYield: an efficient global-search based parametric yield estimation with performance constraints. - Fang Gong; Hao Yu 001; Yiyu Shi 001; Daesoo Kim; Junyan Ren; Lei He 001 (DAC, 2010)

A sideband-suppressed low-power synthesizer for 14-band dual-carrier MB-OFDM UWB transceivers. - Danfeng Chen; Haipeng Fu; Yunfeng Chen; Wei Li 038; Fan Ye 001; Ning Li 007; Junyan Ren (ISCAS, 2010)

A current-mode 6-9GHz UWB transmitter with output power flattening technique. - Yunfeng Chen; Jinhan Fan; Wei Li 038; Ning Li 007; Junyan Ren (ISCAS, 2010)

A fractional-N frequency synthesizer for cellular and short range multi-standard wireless receiver. - Deping Huang; Jin Zhou 001; Wei Li 038; Ning Li 007; Junyan Ren (ISCAS, 2010)

A 0.22 pJ/step subsampling ADC with fast input-tracking sampling and simplified opamp sharing. - Guanghua Shu; Fan Ye 001; Yao Guo; Mingjun Fan; Junyan Ren; Jun Xu 011; Ning Li 007; Cheng Chen (ISCAS, 2010)

Joint estimation and compensation for front-end imperfection in MB-OFDM UWB systems. - Jun Zhou 002; Liang Liu 002; Fan Ye 001; Junyan Ren (ISCAS, 2010)

A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology. - Liang Liu 002; Fan Ye 001; Xiaojing Ma 001; Tong Zhang 002; Junyan Ren (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A low-voltage differential injection locked divider with forward body bias. - Haipeng Fu; Hanchao Zhou; Yangyang Niu; Junyan Ren; Wei Li 038; Ning Li 007 (ASICON, 2011)

A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application. - Qianqian Ha; Fan Ye 001; Chixiao Chen; Xiaoshi Zhu; Mingshuo Wang; Yu-Jing Lin; Ning Li 007; Junyan Ren (ASICON, 2011)

Low phase noise injection-locked doubler-based quadrature CMOS VCO. - Chen Lian; Wei Li 038; Haipeng Fu; Ning Li 007; Junyan Ren (ASICON, 2011)

A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS. - Chen Shu; Guanghua Shu; Jun Xu 011; Fan Ye 001; Junyan Ren (ASICON, 2011)

A 1.2 V 70 mA low drop-out voltage regulator in 0.13 µm CMOS process. - Qin Wu; Wei Li 038; Ning Li 007; Junyan Ren (ASICON, 2011)

Area efficient LDPC decoder design for parallel layered decoding. - Yuan Yao; Fan Ye 001; Junyan Ren (ASICON, 2011)

Class-AB CMOS buffer with floating class-AB control. - Peng Zhang; Fan Ye 001; Junyan Ren (ASICON, 2011)

A 80-400 MHz 74 dB-DR Gm-C low-pass filter with a unique auto-tuning system. - Ting Gao; Wei Li 038; Ning Li 007; Junyan Ren (ASP-DAC, 2011)

A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter. - Deyun Cai; Haipeng Fu; Junyan Ren; Wei Li 038; Ning Li 007; Hao Yu 001; Kiat Seng Yeo (A-SSCC, 2011)

A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation. - Bei Yu; Chixiao Chen; Yu Zhu; Peng Zhang; Yiwen Zhang; Xiaoshi Zhu; Fan Ye 001; Junyan Ren (A-SSCC, 2011)

Nyquist-rate time-interleaved current-steering DAC with dynamic channel matching. - Long Cheng; Fan Ye 001; Hai-Feng Yang; Ning Li 007; Jun Xu 011; Junyan Ren (ISCAS, 2011)

A harmonic-suppressed regenerative divide-by-5 frequency divider for UWB applications. - Haipeng Fu; Deyun Cai; Junyan Ren; Wei Li 038 (ISCAS, 2011)

A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio. - Jin Zhou 001; Wei Li 038; Deping Huang; Chen Lian; Ning Li 007; Junyan Ren (ISCAS, 2011)

A current-mode RF transmitter for 6-9 GHz MB-OFDM UWB application. - Yunfeng Chen; Jinhan Fan; Wei Li 038; Ning Li 007; Junyan Ren (Sci. China Inf. Sci., 2011)

A 6.2-9.5 GHz receiver for Wimedia MB-OFDM and China UWB standard. - Ting Gao; Feng Zhou; Wei Li 038; Fei Lan; Ning Li 007; Junyan Ren (Sci. China Inf. Sci., 2011)

A 5.5mW 80-400MHz Gm-C low pass filter with a unique auto-tuning system. - Ting Gao; Wei Li 038; Yunfeng Chen; Ning Li 007; Junyan Ren (IEICE Electron. Express, 2011)

A 22-mW 2.2%-EVM UWB Transmitter Using On-Chip Transformer and LO Leakage Calibration. - Yunfeng Chen; Renliang Zheng; Haipeng Fu; Wei Li 038; Ning Li 007; Junyan Ren (IEICE Trans. Electron., 2011)

Reconfigurable baseband processing architecture for communication. - Wenqing Lu; Shuang Zhao; Xiaofang Zhou 002; Junyan Ren; Gerald E. Sobelman (IET Comput. Digit. Tech., 2011)

A Parallel Early-Pruned K-Best MIMO Signal Detector Up to 1.9Gb/s. - Liang Liu 002; Junyan Ren; Xiaojing Ma 001; Fan Ye 001 (Wirel. Pers. Commun., 2011)

A low power programmable band-pass filter with novel pseudo-resistor for portable biopotential acquisition system. - Shunli Ma; Changming Chen; Yiwen Zhang; Junyan Ren (APCCAS, 2012)

A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation. - Yiwen Zhang; Xiaoshi Zhu; Chixiao Chen; Fan Ye 001; Junyan Ren (APCCAS, 2012)

Output-dependent delay cancellation technique for high-accuracy current-steering DACs. - Long Cheng; Yu-Jing Lin; Fan Ye 001; Ning Li 007; Junyan Ren (ISCAS, 2012)

A time-to-digital converter based AFC for wideband frequency synthesizer. - Deping Huang; Wei Li 038; Jin Zhou 001; Ning Li 007; Junyan Ren; Jinghong Chen (ISCAS, 2012)

An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling. - Chixiao Chen; ShengChang Cai; Jialiang Xu; Xiaoshi Zhu; Fan Ye 001; Junyan Ren (MWSCAS, 2012)

A digitally calibrated current-steering DAC with current-splitting array. - Long Cheng; Chixiao Chen; Fan Ye 001; Ning Li 007; Junyan Ren (MWSCAS, 2012)

A cancellation technique for output-dependent delay differences in high-accuracy DACs. - Long Cheng; Yu-Jing Lin; Mingshuo Wang; Fan Ye 001; Ning Li 007; Junyan Ren (MWSCAS, 2012)

A 1.2 V 1.0-GS/s 8-bit Voltage-Buffer-Free Folding and interpolating ADC. - Mingshuo Wang; Tao Lin; Fan Ye 001; Ning Li 007; Junyan Ren (MWSCAS, 2012)

Carrier Frequency Offset estimation in the Presence of I/Q Mismatch for Wideband OFDM systems. - Xiaolong Wang; Yuankun Xue; Liang Liu 002; Fan Ye 001; Junyan Ren (MWSCAS, 2012)

A 2.4GHz to 3.86GHz digitally controlled oscillator with 18.5kHz frequency resolution using single PMOS varactor. - Yangyang Niu; Wei Li 038; Ning Li 007; Junyan Ren (IEICE Electron. Express, 2012)

Comments on "Estimation of Carrier Frequency Offset With I/Q Mismatch Using Pseudo-Offset Injection in OFDM Systems". - Xiaolong Wang; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials. - Fang Gong; Xuexin Liu; Hao Yu 001; Sheldon X.-D. Tan; Junyan Ren; Lei He 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique. - Yongzhen Chen; Chixiao Chen; Qiang Zhang; Fan Ye 001; Junyan Ren (ASICON, 2013)

A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator. - Zemin Feng; Chixiao Chen; Fan Ye 001; Jun Xu 011; Junyan Ren (ASICON, 2013)

A novel joint estimation and compensation algorithm for non-idealities of analog front-end in DC-OFDM system. - Jiasen Huang; Hao Chen; Junyan Ren; Fan Ye 001 (ASICON, 2013)

Low-complexity synchronizer used in DC-OFDM UWB system. - Bing Jing; Hao Chen; Fan Ye 001; Ning Li 007; Junyan Ren (ASICON, 2013)

Automatic gain control algorithm with high-speed and double closed-loop in UWB system. - Bing Jing; Yuankun Xue; Fan Ye 001; Ning Li 007; Junyan Ren (ASICON, 2013)

FFT design for OFDM-based cognitive radio using a reconfigurable baseband processing architecture. - Wenqing Lu; Gerald E. Sobelman; Xiaofang Zhou 002; Junyan Ren (ASICON, 2013)

A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC. - Jian Mei; Jixuan Xiang; Huabin Chen; Fan Ye 001; Junyan Ren (ASICON, 2013)

A DLL based low-phase-noise clock multiplier with offset-tolerant PFD. - Yuwen Wang; Fan Ye 001; Junyan Ren (ASICON, 2013)

A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch drivers. - Yuzhong Xiao; Chixiao Chen; Rui Wei; Fan Jiang; Jun Xu 011; Junyan Ren (ASICON, 2013)

A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line. - Shunli Ma; Wei Fei; Hao Yu 001; Junyan Ren (CICC, 2013)

Power efficient SAR ADC with optimized settling technique. - Weiru Gu; Hao Zhou 008; Tao Lin; Zhenyu Wang; Fan Ye 001; Junyan Ren (MWSCAS, 2013)

Beyond-one-cycle loop delay CT ΔΣ modulators with proper rational NTF synthesis and time-interleaved quantizers. - Fan Jiang; Chixiao Chen; Yuzhong Xiao; Jun Xu 011; Junyan Ren (MWSCAS, 2013)

A mixed sample-time error calibration technique in time-interleaved ADCs. - Bei Yu; Chixiao Chen; Fan Ye 001; Junyan Ren (IEICE Electron. Express, 2013)

A 0.13-µm CMOS 0.1-12GHz active balun-LNA for multi-standard applications. - Kaichen Zhang; Wei Li 038; Ning Li 007; Junyan Ren (IEICE Electron. Express, 2013)

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter. - Deyun Cai; Haipeng Fu; Junyan Ren; Wei Li 038; Ning Li 007; Hao Yu 001; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 96-GHz Oscillator by High-Q Differential Transmission Line loaded with Complementary Split-Ring Resonator in 65-nm CMOS. - Wei Fei; Hao Yu 001; Yang Shang; Deyun Cai; Junyan Ren (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1. - Zhenyu Wang; Mingshuo Wang; Weiru Gu; Chixiao Chen; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Carrier Frequency Offset and I/Q Imbalance Compensation for MB-OFDM Based UWB System. - Liang Liu 002; Junyan Ren; Jun Zhou 002; Fan Ye 001 (Wirel. Pers. Commun., 2013)

General expression based inner loop unrolling scheme for TV-GD algorithm adopted in photoacoustic imaging. - Jiasen Huang; Junyan Ren; Jun Xu; Yuanyuan Wang 001 (BioCAS, 2014)

A 131.5GHz, -84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS. - Shunli Ma; Hao Yu 001; Yang Shang; Wei Meng Lim; Junyan Ren (ESSCIRC, 2014)

No zero padded sparse matrix-vector multiplication on FPGAs. - Jiasen Huang; Junyan Ren; Wenbo Yin; Lingli Wang (FPT, 2014)

A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier. - Chixiao Chen; Zemin Feng; Huabin Chen; Mingshuo Wang; Jun Xu 011; Fan Ye 001; Junyan Ren (ISCAS, 2014)

A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators. - Guoxian Dai; Chixiao Chen; Shunli Ma; Fan Ye 001; Junyan Ren (ISCAS, 2014)

An overview of new design techniques for high performance CMOS millimeter-wave circuits. - Shunli Ma; Junyan Ren; Hao Yu 001 (ISIC, 2014)

A 7 bit 1 GS/s pipelined folding and interpolating ADC with coarse-stage-free joint encoding. - Mingshuo Wang; Li Lin; Fan Ye 001; Junyan Ren (IEICE Electron. Express, 2014)

A 42fJ 8-bit 1.0-GS/s folding and interpolating ADC with 1GHz signal bandwidth. - Mingshuo Wang; Fan Ye 001; Wei Li 038; Junyan Ren (IEICE Electron. Express, 2014)

Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer. - Wei Fei; Hao Yu 001; Haipeng Fu; Junyan Ren; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL. - Fazhi An; Shunli Ma; Qian Chen; Guangyao Zhou; Fan Ye 001; Junyan Ren (ASICON, 2015)

A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology. - Qian Chen; Fazhi An; Guangyao Zhou; Shunli Ma; Fan Ye 001; Junyan Ren (ASICON, 2015)

A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method. - Zemin Feng; Jingjing Wang; Chixiao Chen; Jun Xu 011; Junyan Ren (ASICON, 2015)

LVDS transmitter with optimized high power-efficiency 8: 1 MUX. - Yuan Su; Yimin Wu; Qiang Zhang; Xuerong Zhou; Fan Ye 001; Junyan Ren (ASICON, 2015)

100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array. - Jingjing Wang; Rongjin Xu; Chixiao Chen; Fan Ye 001; Jun Xu 011; Junyan Ren (ASICON, 2015)

An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units. - Weizhen Wang; Hao Zhou 008; Fan Ye 001; Junyan Ren (ASICON, 2015)

A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network. - Rongjin Xu; Yongzhen Chen; Mingshuo Wang; Ning Li 007; Fan Ye 001; Junyan Ren (ASICON, 2015)

A 100MS/s 5bit fully digital flash ADC with standard cells. - Xiangyan Xue; Xuerong Zhou; Fan Ye 001; Junyan Ren (ASICON, 2015)

I/Q imbalance estimation in OFDM systems. - Xuerong Zhou; Xiangyan Xue; Fan Ye 001; Junyan Ren (ASICON, 2015)

A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS. - Guangyao Zhou; Shunli Ma; Fazhi An; Ning Li 007; Fan Ye 001; Junyan Ren (ASICON, 2015)

A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. - Shunli Ma; Guangyao Zhou; Jianbing Jiang; Chixiao Chen; Yongzhen Chen; Fan Ye 001; Junyan Ren (ESSCIRC, 2015)

Greedy approach based heuristics for partitioning SpMxV on FPGAs. - Jiasen Huang; Weina Lu; Junyan Ren (FPL, 2015)

A 270-MS/s 6-b SAR ADC with preamplifier sharing and self-locking comparators. - Chixiao Chen; Jixuan Xiang; Jiang Fan; Xu Jun; Ye Fan 001; Junyan Ren (IEICE Electron. Express, 2015)

Switch-back based on charge equalization switching technique for SAR ADC. - Weiru Gu; Fan Ye 001; Junyan Ren (IEICE Electron. Express, 2015)

A high power-efficient LVDS output driver with adjustable feed-forward capacitor compensation. - Yuan Su; Fan Ye 001; Junyan Ren (IEICE Electron. Express, 2015)

Greedy Approach Based Heuristics for Partitioning Sparse Matrices. - Jiasen Huang; Junyan Ren; Wei Li 038 (IEICE Trans. Inf. Syst., 2015)

A Monolithic Sub-sampling PLL based 6-18 GHz Frequency Synthesizer for C, X, Ku Band Communication. - Hanchao Zhou; Ning Zhu; Wei Li 038; Zibo Zhou; Ning Li 007; Junyan Ren (IEICE Trans. Electron., 2015)

An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators. - Chixiao Chen; Zemin Feng; Jun Xu 011; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network. - Bingwei Jiang; Chixiao Chen; Junyan Ren; Howard C. Luong (A-SSCC, 2016)

Transformer-based varactor-less 96GHz-110GHz VCO and 89GHz-101GHz QVCO in 65nm CMOS. - Xiaolong Liu; Chixiao Chen; Junyan Ren; Howard C. Luong (A-SSCC, 2016)

A proved dither-injection method for memory effect in double sampling pipelined ADC. - Fubiao Cao; Yongzhen Chen; Yuefeng Cao; Fan Ye 001; Junyan Ren (ASICON, 2017)

An input buffer for 12bit 2GS/s ADC. - Fubiao Cao; Yongzhen Chen; Zhiyuan Dai; Fan Ye 001; Junyan Ren (ASICON, 2017)

A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error. - Xiaoqing Chen; Fan Ye 001; Junyan Ren (ASICON, 2017)

A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs. - Yongzhen Chen; Yimin Wu; Fubiao Cao; Fan Ye 001; Junyan Ren (ASICON, 2017)

A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC. - Zhiyuan Dai; Hang Hu 003; Manxin Li; Fan Ye 001; Junyan Ren (ASICON, 2017)

A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique. - Hang Hu 003; Zhiyuan Dai; Manxin Li; Fan Ye 001; Junyan Ren (ASICON, 2017)

A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation. - Hang Hu 003; Manxin Li; Zhiyuan Dai; Fan Ye 001; Junyan Ren (ASICON, 2017)

A 12bit asynchronous SAR-incremental sub-range ADC. - Manxin Li; Hang Hu 003; Zhiyuan Dai; Fan Ye 001; Junyan Ren (ASICON, 2017)

A stacked-packaged 16-channel ADC for ultrasound application. - Yimin Wu; Yongzhen Chen; Manxin Li; Fan Ye 001; Junyan Ren (ASICON, 2017)

A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS. - Shunli Ma; Jili Sheng; Ning Li 007; Junyan Ren (A-SSCC, 2017)

A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier. - Yongzhen Chen; Jingjing Wang; Hang Hu 003; Fan Ye 001; Junyan Ren (ISCAS, 2017)

High speed digital ELD compensation with hybrid thermometer coding in CT ΔΣ modulators. - Hang Hu 003; Zemin Feng; Chixiao Chen; Fan Ye 001; Junyan Ren (MWSCAS, 2017)

An improved ring amplifier with process- and supply voltage-insensitive dead-zone. - Yuefeng Cao; Yongzhen Chen; Tianli Zhang; Fan Ye 001; Junyan Ren (MWSCAS, 2017)

Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{ mathrm {cm}}$ -Based Switching. - Dezhi Xing; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Fan Ye 001; Junyan Ren; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC. - Yuefeng Cao; Yongzhen Chen; Zhekan Ni; Fan Ye 001; Junyan Ren (APCCAS, 2018)

An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs. - Yuefeng Cao; Tianli Zhang; Yongzhen Chen; Fan Ye 001; Junyan Ren (ISCAS, 2018)

A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation. - Yongzhen Chen; Zhekan Ni; Yuefeng Cao; Fan Ye 001; Junyan Ren (ISCAS, 2018)

A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC. - Manxin Li; Yongzhen Chen; Fan Ye 001; Junyan Ren (ISCAS, 2018)

Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC. - Tianli Zhang; Yuefeng Cao; Fan Ye 001; Junyan Ren (ISCAS, 2018)

A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches. - Zhiyuan Dai; Hang Hu 003; Yongzhen Chen; Fan Ye 001; Junyan Ren (MWSCAS, 2018)

A Third-order Band-pass Fully-passive Noise-Shaping Modulator Based on a Time-interleaved SAR ADC. - Zhiyuan Dai; Hang Hu 003; Yimin Wu; Fan Ye 001; Junyan Ren (MWSCAS, 2018)

Low Power Low Noise Amplifier with DC Offset Correction at 1 V Supply Voltage for Ultrasound Imaging Systems. - Longheng Luo; Yimin Wu; Jianguo Diao; Fan Ye 001; Junyan Ren (MWSCAS, 2018)

An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration. - Yongzhen Chen; Fan Ye 001; Junyan Ren (Microelectron. J., 2018)

A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier. - Yongzhen Chen; Jingjing Wang; Hang Hu 003; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 5-to-8-GHz Wideband Miniaturized Dielectric Spectroscopy Chip With $I/Q$ Mismatch Calibration in 65-nm CMOS. - Shunli Ma; Ning Li 007; Junyan Ren (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 40Gb/s Low Power Transmitter with 2-tap FFE and 40: 1 MUX in 28nm CMOS Technology. - Wenbin He; Fan Ye 001; Junyan Ren (ASICON, 2019)

A Comparator-Reused Dynamic-Amplifier for Noise-Shaping SAR ADC. - Longheng Luo; Xingchen Shen; Jianguo Diao; Fan Ye 001; Junyan Ren (ASICON, 2019)

A 22-40.5 GHz UWB LNA Design in 0.15um GaAs. - Dong Wei 008; Jincheng Zhang; Tianxiang Wu; Shunli Ma; Junyan Ren (ASICON, 2019)

A 36-40 GHz VCO with bonding inductors for millimeter wave 5G Communication. - Tianxiang Wu; Jincheng Zhang; Dong Wei 008; Lihe Nie; Yuting Yao; Shunli Ma; Junyan Ren (ASICON, 2019)

SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors. - Yuting Yao; Manxin Li; Tianxiang Wu; Hu Xu; Shunli Ma; Wenzhong Bao; Junyan Ren (ASICON, 2019)

A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers. - Yuting Yao; Jipeng Wei; Manxin Li; Shunli Ma; Fan Ye 001; Junyan Ren (ASICON, 2019)

A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period. - Shumin Zhang; Yuefeng Cao; Fan Ye 001; Junyan Ren (ASICON, 2019)

A 130-150 GHz Power Amplifier for Millimeter Wave Imaging in 65-nm CMOS. - Jincheng Zhang; Lihe Nie; Dong Wei 008; Tianxiang Wu; Shunli Ma; Junyan Ren (ASICON, 2019)

A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps. - Yongzhen Chen; Xingchen Shen; Zhekan Ni; Jingchao Lan; Chixiao Chen; Fan Ye 001; Junyan Ren (ESSCIRC, 2019)

Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR. - Tianli Zhang; Yuefeng Cao; Shumin Zhang; Chixiao Chen; Fan Ye 001; Junyan Ren (ESSCIRC, 2019)

A 13-bit 180-MS/s SAR ADC with Efficient Capacitor-Mismatch Estimation and Dither Enhancement. - Fan Ye 001; Shuai Li 014; Min Zhu; Zhekan Ni; Junyan Ren (ISCAS, 2019)

A Capacitively-Degenerated High-Linearity Dynamic Amplifier using a Real-Time Gain Detection Technique. - Longheng Luo; Yimin Wu; Jipeng Wei; Fan Ye 001; Junyan Ren (ISCAS, 2019)

A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration. - Jipeng Wei; Yuting Yao; Longheng Luo; Shunli Ma; Fan Ye 001; Junyan Ren (ISCAS, 2019)

Energy-Efficient Analog Frond-End Design for Ultrasound Imaging Applications. - Jianguo Diao; Shuai Li 014; Yimin Wu; Fan Ye 001; Jun Xu 019; Junyan Ren (MWSCAS, 2019)

A 20MHz Bandwidth Band-Pass Noise-Shaping SAR ADC With OPAMP Sharing Switched-Capacitor Filter. - Shuai Li 014; Jianguo Diao; Yimin Wu; Fan Ye 001; Junyan Ren (MWSCAS, 2019)

A Band-Pass Noise-Shaping Modulator Using the Error-Feedback Structure on a 10-bit SAR ADC. - Longheng Luo; Shuai Li 014; Jipeng Wei; Yimin Wu; Fan Ye 001; Junyan Ren (MWSCAS, 2019)

A 140 GHz, 4 dB Noise-Figure Low-Noise Amplifier Design with the Compensation of Parasitic Capacitance CGS. - Dong Wei 008; Xuan Ding; Hai Yu; Bo Yu; Shunli Ma; Qun Jane Gu; Junyan Ren (MWSCAS, 2019)

A Ring Amplifier Based Current Feedback Continuous Time PGA for High Frequency Ultrasound Applications. - Yimin Wu; Jingchao Lan; Shuai Li 014; Fan Ye 001; Junyan Ren (MWSCAS, 2019)

A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. - Zhekan Ni; Yongzhen Chen; Fan Ye 001; Junyan Ren (Microelectron. J., 2019)

3D FEM Analysis of High-Frequency AlN-Based PMUT Arrays on Cavity SOI. - Wenjuan Liu; Leming He; Xubo Wang; Jia Zhou; Weijiang Xu; Nikolay Smagin; Malika Toubal; Hao Yu 001; Yuandong Gu; Jinghui Xu; Denis Remiens; Junyan Ren (Sensors, 2019)

A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package. - Shunli Ma; Hao Yu 001; Qun Jane Gu; Junyan Ren (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network. - Min Chen 036; Yimin Wu; Jingchao Lan; Fan Ye 001; Chixiao Chen; Junyan Ren (APCCAS, 2020)

A Low Power Reference Voltage Buffer and High Density Unit capacitor in a 12b 200MS/s SAR ADC. - Wenbin He; Ziwei Li; Fan Ye 001; Junyan Ren (APCCAS, 2020)

A Low-Power Low-Noise Dynamic Comparator With Latch-Embedding Floating Amplifier. - Ziwei Li; Wenbin He; Fan Ye 001; Junyan Ren (APCCAS, 2020)

A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems. - Yimin Wu; Jingchao Lan; Min Chen 036; Fan Ye 001; Junyan Ren (APCCAS, 2020)

An Area-Power-Efficient AFE with NS-SAR ADC For High-Frequency Ultrasound Applications. - Yimin Wu; Shuai Li 014; Longheng Luo; Fan Ye 001; Junyan Ren (APCCAS, 2020)

A 13 Bit 100 MS/s SAR ADC with 74.57 dB SNDR in 14-nm CMOS FinFET. - Yan Zheng; Fan Ye 001; Junyan Ren (ISCAS, 2020)

A Fast Response Reference Voltage Buffer for 12b 200MS/s SAR ADC. - Wenbin He; Fan Ye 001; Junyan Ren (MWSCAS, 2020)

A 12-bit SAR ADC Using Pseudo-Dynamic Weighting C-DAC for Capacitor Error Calibration. - Fan Ye 001; Junyan Ren (MWSCAS, 2020)

A 10-18 GHz GaN Power Amplifier Based on Asymmetric Magnetically Coupled Resonator. - Jincheng Zhang; Lihe Nie; Shunli Ma; Junyan Ren (MWSCAS, 2020)

Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS2 Materials With Physical and SPICE Model. - Shunli Ma; Yan Wang 097; Xinyu Chen; Tianxiang Wu; Xi Wang; Hongwei Tang; Yuting Yao; Hao Yu 001; Yaochen Sheng; Jingyi Ma; Junyan Ren; Wenzhong Bao (IEEE Access, 2020)

A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC. - Shunli Ma; Tianxiang Wu; Junyan Ren (IEEE Access, 2020)

A 79GHz 5-bit Phase Shifter With π-Network in 28-nm CMOS. - Xu Chen; Junyan Ren; Shunli Ma (ASICON, 2021)

A High Linearity and Low Noise Anti-Aliasing Filter for ADCs. - Hao Chi; Jun Xu; Fan Ye 001; Junyan Ren (ASICON, 2021)

A Wide-Range 12b 150MS/s P-SAR ADC with Open-Loop Residue Amplifier for Ultrasound AFE. - Ziwei Li; Yutong Zhao; Guoyao Wu; Fan Ye 001; Junyan Ren (ASICON, 2021)

A Three-Stage Comparator with High Speed and Low Power. - Jingqi Wang; Fan Ye 001; Junyan Ren (ASICON, 2021)

An 4th-order N-path Bandpass Filter with a Tuning Range of 1-30 GHz and OOB Rejection > 30 dB in 28 nm CMOS. - Xi Wang; Junyan Ren; Shunli Ma (ASICON, 2021)

A 5-bit High-Linearity, Binary-Recombination-Redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC. - Guoyao Wu; Ziwei Li; Yutong Zhao; Fan Ye 001; Junyan Ren (ASICON, 2021)

A C-Band Power Amplifier with Over-Neutralization Technique and Coupled-Line MCR Matching Methods for 5G Communication in 0.25-μm GaAs. - Zhiyang Zhang; Junyan Ren; Shunli Ma (ASICON, 2021)

A 68.36 dB 12 bit 100MS/s SAR ADC with a low-noise comparator in 14-nm CMOS FinFet. - Yan Zheng; Jingchao Lan; Fan Ye 001; Junyan Ren (ASICON, 2021)

A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process. - Jincheng Zhang; Tianxiang Wu; Yong Chen 005; Junyan Ren; Shunli Ma (A-SSCC, 2021)

A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio. - Dong Wei 008; Tianxiang Wu; Shunli Ma; Yong Chen 005; Junyan Ren (ESSCIRC, 2021)

A Partially Binarized and Fixed Neural Network Based Calibrator for SAR-Pipelined ADCs Achieving 95.0-dB SFDR. - Min Chen 036; Yutong Zhao; Nuo Xu; Fan Ye 001; Junyan Ren (ISCAS, 2021)

An 11-Bit 500 MS/s Two-Step SAR ADC with Non-Attenuated Passive Residue Transfer. - Wenbin He; Fan Ye 001; Junyan Ren (ISCAS, 2021)

A High Linearity Bootstrapped Switch with Leakage Current Suppressed for GS/s Sampling Rate ADC. - Jingchao Lan; Yan Zheng; Yimin Wu; Min Chen 036; Fan Ye 001; Junyan Ren (ISOCC, 2021)

Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCs. - Ziwei Li; Guoyao Wu; Yutong Zhao; Fan Ye 001; Junyan Ren (ISOCC, 2021)

Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration. - Danfeng Zhai; Chixiao Chen; Liang Qi 002; Fan Ye 001; Junyan Ren (ISOCC, 2021)

A Hardware-Efficient Calibrator for SAR-Pipelined ADCs with a Layer-based Sharing Neural Network. - Min Chen 036; Nuo Xu; Yutong Zhao; Fan Ye 001; Junyan Ren (MWSCAS, 2021)

A Novel Ring Amplifier with Low Common-Mode Voltage Variation and Noise Reduction Using Floating Power Technique. - Jingchao Lan; Yan Zheng; Yimin Wu; Fan Ye 001; Junyan Ren (MWSCAS, 2021)

Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization. - Danfeng Zhai; Peizhe Li; Jiushan Zhang; Chixiao Chen; Fan Ye 001; Junyan Ren (MWSCAS, 2021)

A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS. - Manxin Li; Yuting Yao; Biao Hu; Jipeng Wei; Yong Chen 005; Shunli Ma; Fan Ye 001; Junyan Ren (IEEE Access, 2021)

Analysis and Design of a 35-GHz Hybrid π-Network High-Gain Phase Shifter With 360° Continuous Phase Shifting. - Dong Wei 008; Xuan Ding; Hai Yu; Yen-Cheng Kuan; Qun Jane Gu; Zhiwei Xu 003; Shunli Ma; Junyan Ren (IEEE Access, 2021)

A 120-150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm Psat for Sub-THz Imaging System. - Jincheng Zhang; Tianxiang Wu; Lihe Nie; Shunli Ma; Yong Chen 005; Junyan Ren (IEEE Access, 2021)

A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET. - Yan Zheng; Jingchao Lan; Fan Ye 001; Junyan Ren (IEEE Access, 2021)

Development of Broadband High-Frequency Piezoelectric Micromachined Ultrasonic Transducer Array. - Xubo Wang; Leming He; You-Cao Ma; Wenjuan Liu; Weijiang Xu; Junyan Ren; Antoine Riaud; Jia Zhou (Sensors, 2021)

A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. - Yuefeng Cao; Shumin Zhang; Tianli Zhang; Yongzhen Chen; Yutong Zhao; Chixiao Chen; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 5G Wireless Event-Driven Sensor Chip for Online Power-Line Disturbances Detecting Network in 0.25 μm GaAs Process. - Shunli Ma; Tianxiang Wu; Jincheng Zhang; Junyan Ren (IEEE Trans. Ind. Electron., 2021)

A Low Noise TIA with Continuous Time-Gain Compensation for Ultrasound Transducers. - Xinwei Yu; Fan Ye 001; Junyan Ren (APCCAS, 2022)

A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE. - Zhiyang Zhang; Xi Wang; Yong Chen 005; Junyan Ren; Shunli Ma (APCCAS, 2022)

A 500-MS/s 9-Bit Time-Domain ADC Using a Nonbinary Successive Approximation TDC. - Yutong Zhao; Fan Ye 001; Junyan Ren (APCCAS, 2022)

A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration. - Jingchao Lan; Danfeng Zhai; Yongzhen Chen; Zhekan Ni; Xingchen Shen; Fan Ye 001; Junyan Ren (ISCAS, 2022)

A Two-Way Current-Combining W-band Power Amplifier Achieving 17.4-dBm Output Power with 19.4% PAE in 65-nm Bulk CMOS. - Zhiyang Zhang; Xi Wang; Junyan Ren; Shunli Ma (ISCAS, 2022)

A Single-Channel 1.25-GS/s 11-bit Pipelined ADC with Robust Floating-Powered Ring Amplifier and First-Order Gain Error Calibration. - Jingchao Lan; Yuxuan Zhang; Fan Ye 001; Junyan Ren (MWSCAS, 2022)

A Branch-Gain-Balanced LNA Based on Voltage- Controlled Resistor Feedback and Shared CMFB Amplifier. - Lulu Liu; Yimin Wu; Xinwei Yu; Fan Ye 001; Junyan Ren (MWSCAS, 2022)

A Broadband LMS-based Band-split Crosstalk Cancellation Method for Ultrasound Systems. - Wenhan Lu; Yimin Wu; Fan Ye 001; Junyan Ren (MWSCAS, 2022)

A 134-154 GHz Low-Noise Amplifier Achieving 36.3-dB Maximum Gain with 3.8-dB Minimum Noise Figure for D-Band Imaging System. - Xi Wang; Zhiyang Zhang; Junyan Ren; Shunli Ma (MWSCAS, 2022)

A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology. - Tianxiang Wu; Xi Wang; Yong Chen 005; Junyan Ren; Shunli Ma (Int. J. Circuit Theory Appl., 2022)

A 23- to 28-GHz 5-bit switch-type phase shifter with 1-bit calibration based on optimized ABCD matrix design methods for 5G MIMO system in 0.15-μm GaAs. - Zhiyang Zhang; Lihe Nie; Jincheng Zhang; Tianxiang Wu; Yong Chen 005; Junyan Ren; Shunli Ma (Int. J. Circuit Theory Appl., 2022)

Sensitivity - Bandwidth Optimization of PMUT with Acoustical Matching Using Finite Element Method. - Leming He; Weijiang Xu; Yan Wang 097; Jia Zhou; Junyan Ren (Sensors, 2022)

High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. - Danfeng Zhai; Wenning Jiang; Xinru Jia; Jingchao Lan; Mingqiang Guo; Sai-Weng Sin; Fan Ye 001; Qi Liu 010; Junyan Ren; Chixiao Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation. - Jingchao Lan; Yongzhen Chen; Xingchen Shen; Zhekan Ni; Yimin Wu; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 6.5-mm2 10.5-to-15.5-GHz Differential GaN PA With Coupled-Line-Based Matching Networks Achieving 10-W Peak Psat and 42% PAE. - Jincheng Zhang; Lihe Nie; Yong Chen 005; Junyan Ren; Shunli Ma (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology. - Bingrong Lyu; Fan Ye 001; Junyan Ren (ASICON, 2023)

A Multi-channel 12-bits 100MS/s SAR ADC in 65nm CMOS. - Yigang Wei; Tianxiang Wu; Shunli Ma; Junyan Ren (ASICON, 2023)

A 15GHz Class-C VCO with Two-stage Buffer in 0.15-μm GaAs. - Lei Wu; Junyan Ren; Tianxiang Wu; Shunli Ma (ASICON, 2023)

A Three-stage Analog Low-Frequency Drift Calibration and DC Offset Correction Circuit for Ultrasonic AFE. - Siqing Wu; Xinwei Yu; Xingtao Zhu; Fan Ye 001; Junyan Ren (ASICON, 2023)

A 300MS/s 57.6dB SNDR Single-Channel SAR ADC with Accelerated SAR Logic. - Muxi Zou; Shunli Ma; Xiaodi Feng; Junyan Ren; Tianxiang Wu (ASICON, 2023)

A 400-MS/s 12-bit Voltage-Time Hybrid ADC with a Ping-Pong SAR TDC for Speed Enhancement. - Yutong Zhao; Yuguo Xiang; Fan Ye 001; Junyan Ren (ISCAS, 2023)

A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique. - Yujia Wang; Jincheng Zhang; Yong Chen 005; Junyan Ren; Shunli Ma (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor. - Xi Wang; Dong Wei 008; Zhiyang Zhang; Tianxiang Wu; Xu Chen; Yong Chen 005; Junyan Ren; Shunli Ma (Int. J. Circuit Theory Appl., 2023)

Low-Noise Low-Power Ultrasound AFE With Continuous TGC Built in Both TIA and Beamformer. - Xinwei Yu; Yan Wang 097; Fan Ye 001; Junyan Ren (IEEE Trans. Biomed. Circuits Syst., 2023)

28-nm CMOS Ultrasound AFE With Split Attenuation for Optimizing Gain-Range, Noise, and Area. - Xinwei Yu; Zhi Chen; Siqing Wu; Lulu Liu; Hao Chi; Fan Ye 001; Junyan Ren (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Hardware-Implemented Calibration Based on Sinusoidal Fitting for Hybrid Pipeline ADC. - Yuguo Xiang; Yutong Zhao; Dayan Zhou; Danfeng Zhai; Junyan Ren; Fan Ye 001 (ISCAS, 2024)

A 3.0-V 4.2-μA 2.23-ppm/°C BGR with cross-connected NPNs and base-current compensation. - Weidong Xue; Xinwei Yu; Yisen Zhang; Xin Ming; Jian Fang; Junyan Ren (Microelectron. J., 2024)

A 4.8dB NF, 3-to-119GHz Distributed LNA With Three-Turn Transformer and Multiple Magnetic Coupling Feedback Network in 28nm CMOS. - Yujia Wang; Jincheng Zhang; Shunli Ma; Junyan Ren (ISCAS, 2025)

An Effective Digital Calibration Method Based on Volterra Neural Network for Pipeline ADCs. - Yuguo Xiang; Danfeng Zhai; Junyan Ren; Fan Ye 001 (ISCAS, 2025)

A 24V-to-1V Triple Series-Capacitor Buck Converter With Low-Voltage Power Switches. - Weidong Xue; Xinwei Yu; Yisen Zhang; Junyan Ren (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Harmonic-Suppressed GaN Power Amplifier Using Artificial Coupled Resonator. - Letian Guo; Jincheng Zhang; Lihe Nie; Jian Wang; Yong Chen 005; Junyan Ren; Shunli Ma (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Comprehensive Digital Calibration for Pipelined ADCs Using Cascaded Nonlinearity Correction. - Yuguo Xiang; Dayan Zhou; Minjia Song; Danfeng Zhai; Jingchao Lan; Junyan Ren; Fan Ye 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)