Junyoung Park
Affiliations:- Korea Advanced Institute of Science and Technology, Department of Electrical Engineering, Korea
According to our database1,
Junyoung Park
authored at least 35 papers
between 2010 and 2023.
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Bibliography
2023
CoRR, 2023
2021
Sensors, 2021
2020
Sensors, 2020
2016
A 0.5 V 54 µW Ultra-Low-Power Object Matching Processor for Micro Air Vehicle Navigation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
An Energy-Efficient Embedded Deep Neural Network Processor for High Speed Visual Attention in Mobile Vision Recognition SoC.
IEEE J. Solid State Circuits, 2016
14.1 A 126.1mW real-time natural UI/UX processor with embedded deep-learning core for low-power smart glasses.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
An energy-efficient parallel multi-core ADAS processor with robust visual attention and workload-prediction DVFS for real-time HD stereo stream.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
2015
An Energy-Efficient and Scalable Deep Learning/Inference Processor With Tetra-Parallel MIMD Architecture for Big Data Applications.
IEEE Trans. Biomed. Circuits Syst., 2015
A Vocabulary Forest Object Matching Processor With 2.07 M-Vector/s Throughput and 13.3 nJ/Vector Per-Vector Energy for Full-HD 60 fps Video Object Recognition.
IEEE J. Solid State Circuits, 2015
Intelligent task scheduler with high throughput NoC for real-time mobile object recognition SoC.
Proceedings of the ESSCIRC Conference 2015, 2015
A 1.9nJ/pixel embedded deep neural network processor for high speed visual attention in a mobile vision recognition SoC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
Intelligent Network-on-Chip With Online Reinforcement Learning for Portable HD Object Recognition Processor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A Vocabulary Forest-based object matching processor with 2.07M-vec/s throughput and 13.3nJ/vector energy in full-HD resolution.
Proceedings of the Symposium on VLSI Circuits, 2014
A 1.5nJ/pixel super-resolution enhanced FAST corner detection processor for high accuracy AR.
Proceedings of the ESSCIRC 2014, 2014
A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014
2013
A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams.
IEEE J. Solid State Circuits, 2013
A 646GOPS/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognition.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A multi-modal and tunable Radial-Basis-Funtion circuit with supply and temperature compensation.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A 34.1fps scale-space processor with two-dimensional cache for real-time object recognition.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A high-throughput 16× super resolution processor for real-time object recognition SoC.
Proceedings of the ESSCIRC 2013, 2013
A multi-granularity parallelism object recognition processor with content-aware fine-grained task scheduling.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013
2012
IEEE Micro, 2012
A 92-mW Real-Time Traffic Sign Recognition System With Robust Illumination Adaptation and Support Vector Machine.
IEEE J. Solid State Circuits, 2012
A 320mW 342GOPS real-time moving object recognition processor for HD 720p video streams.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A simultaneous multithreading heterogeneous object recognition processor with machine learning based dynamic resource management.
Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
A 345 mW Heterogeneous Many-Core Processor With an Intelligent Inference Engine for Robust Object Recognition.
IEEE J. Solid State Circuits, 2011
A 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
A 92mW real-time traffic sign recognition system with robust light and dark adaptation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
A 118.4 GB/s Multi-Casting Network-on-Chip With Hierarchical Star-Ring Combined Topology for Real-Time Object Recognition.
IEEE J. Solid State Circuits, 2010
A 345mW heterogeneous many-core processor with an intelligent inference engine for robust object recognition.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A 30fps stereo matching processor based on belief propagation with disparity-parallel PE array architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Intelligent NoC with neuro-fuzzy bandwidth regulation for a 51 IP object recognition processor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010