Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application. - Jabeom Koo; Gil-Su Kim; Junyoung Song; Kwan-Weon Kim; Young-Jung Choi; Chulwoo Kim (CICC, 2009)

A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13µm CMOS. - Sewook Hwang; Inhwa Jung; Junyoung Song; Chulwoo Kim (ISCAS, 2012)

A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. - Hyun-Woo Lee; Soo-Bin Lim; Junyoung Song; Jabeom Koo; Dae-Han Kwon; Jong-Ho Kang; Yunsaing Kim; Young-Jung Choi; Kunwoo Park; Byong-Tae Chung; Chulwoo Kim (ISSCC, 2012)

A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process. - Junyoung Song; Hyun-Woo Lee; Sewook Hwang; Inhwa Jung; Chulwoo Kim (ASP-DAC, 2013)

An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface. - Junyoung Song; Hyun-Woo Lee; Soo-Bin Lim; Sewook Hwang; Yunsaing Kim; Young-Jung Choi; Byong-Tae Chung; Chulwoo Kim (ISSCC, 2013)

A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface. - Soo-Bin Lim; Hyun-Woo Lee; Junyoung Song; Chulwoo Kim (IEEE J. Solid State Circuits, 2013)

A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection. - Junyoung Song; Inhwa Jung; Minyoung Song; Young-Ho Kwak; Sewook Hwang; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip. - Phi-Hung Pham; Junyoung Song; Jongsun Park 001; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2013)

25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. - Hyun-Woo Lee; Junyoung Song; Sangah Hyun; Seunggeun Baek; Yuri Lim; Jungwan Lee; Minsu Park; Haerang Choi; Changkyu Choi; Jin-Youp Cha; Jaeil Kim; Hoon Choi; et al. (ISSCC, 2014)

A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process. - Junyoung Song; Sewook Hwang; Hyun-Woo Lee; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator. - Kyeong-Min Kim; Sewook Hwang; Junyoung Song; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2014)

High-Bandwidth Memory Interface - Chulwoo Kim; Hyun-Woo Lee; Junyoung Song (Springer, 2014)

17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. - Junyoung Song; Hyun-Woo Lee; Jayoung Kim; Sewook Hwang; Chulwoo Kim (ISSCC, 2015)

A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE. - Sewook Hwang; Sungjun Moon; Junyoung Song; Chulwoo Kim (VLSI Circuits, 2016)

An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers. - Sewook Hwang; Junyoung Song; Sang-Geun Bae; Yeonho Lee 002; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels. - Junyoung Song; Sewook Hwang; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. - Yeonho Lee 002; Yoonjae Choi; Sang-Geun Bae; Jaehun Jun; Junyoung Song; Sewook Hwang; Chulwoo Kim (ISSCC, 2017)

A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques. - Sewook Hwang; Junyoung Song; Yeonho Lee 002; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier. - Jayoung Kim; Junyoung Song; Jungtaek You; Sewook Hwang; Sang-Geun Bae; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM. - Jungtaek You; Junyoung Song; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. - Junyoung Song; Hyun-Woo Lee; Sewook Hwang; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces. - Junyoung Song; Sewook Hwang; Hyun-Woo Lee; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface. - Hyunsu Park; Junyoung Song; Yeonho Lee 002; Jincheol Sim; Jonghyuck Choi; Chulwoo Kim (ISSCC, 2019)

12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. - Yeonho Lee 002; Yoonjae Choi; Junyoung Song; Sewook Hwang; Sang-Geun Bae; Jaehun Jun; Chulwoo Kim (IEEE J. Solid State Circuits, 2019)

A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth. - Sang-Geun Bae; Sewook Hwang; Junyoung Song; Yeonho Lee 002; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 9 Gb/s/ch Transceiver With Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces. - Junyoung Song; Yongtae Kim; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 28Gb/s quad-rate 1-FIR 2-IIR DFE with 20dB Loss Compensation in 65nm CMOS Process. - Yunha Kang; Seung-Myeong Yu; Jongchan An; Wooyoung Choi; Junyoung Song (ICEIC, 2021)

A 20Gb/s/pin Single-ended Transmitter with FEXT Compensation Technique. - Seung-Myeong Yu; Yunha Kang; Wooyoung Choi; Jongchan An; Junyoung Song (ICEIC, 2021)

Digital LDO with reference-less adaptive CLK generation and bit-shifting Coarse-Fine-control. - Wooyoung Choi; Seung-Myeong Yu; Yunha Kang; Junyoung Song (ISOCC, 2021)

A 20-Gb/s Digitally Adaptive Linear Equalizer with 25dB loss for Single-ended Interfaces in 65nm CMOS. - Yunha Kang; Junyoung Song (ISOCC, 2021)

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process. - Yunha Kang; Junyoung Song (IEICE Electron. Express, 2021)

30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links. - Hyunsu Park; Junyoung Song; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Jeongsik Yoo; Chulwoo Kim (IEEE J. Solid State Circuits, 2021)

A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology. - Junyoung Song; Sewook Hwang; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces. - Hyunsu Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Youngwook Kwon; Junyoung Song; Chulwoo Kim (ISSCC, 2022)

Segmented Match-Line and Charge-Sharing Based Low-Cost TCAM. - Minseob Shim; Junwon Jeong; Junyoung Song; Yongtae Kim; Woong Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Digital LDO with Adaptive Loop Control and Reset-Voltage Optimization for Comparator. - Gwangmyeong An; Juneho Yoon; Taeho Kim; Hyunsu Jang; Myeongju Park; Bongsu Kim; Jongchan An; Junyoung Song (ISOCC, 2023)

An 11 Gb/s 0.376 pJ/Bit Capacitor-Less Dicode Transceiver With Pattern-Dependent Equalizations TIA Termination for Parallel DRAM Interfaces. - Hyunsu Park; Seung-Myeong Yu; Junyoung Song (IEEE Access, 2024)

A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit. - Jongchan An; Seung-Myeong Yu; Gwangmyeong An; Bongsu Kim; Hyunsu Jang; Sewook Hwang; Junyoung Song (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 1.58 pJ/b 9 G bps Reference-Less Clock and Data Recovery Circuit With Sigma Range Detector. - Jongchan An; Seung-Myeong Yu; Gwangmyeong An; Songi Cheon; Hyunsu Jang; Junyoung Song (IEEE Trans. Circuits Syst. II Express Briefs, 2025)