Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA. - Tao Xiao; Yuran Qiao; Junzhong Shen; Qianming Yang; Mei Wen (ICA3PP (1), 2015)

Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA. - Yuran Qiao; Junzhong Shen; Dafei Huang; Qianming Yang; Mei Wen; Chunyuan Zhang (NPC, 2017)

FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency. - Yuran Qiao; Junzhong Shen; Tao Xiao; Qianming Yang; Mei Wen; Chunyuan Zhang (Concurr. Comput. Pract. Exp., 2017)

Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA. - Junzhong Shen; You Huang; Zelong Wang; Yuran Qiao; Mei Wen; Chunyuan Zhang (FPGA, 2018)

Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. - Junzhong Shen; Yuran Qiao; You Huang; Mei Wen; Chunyuan Zhang (ISCAS, 2018)

MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA. - You Huang; Junzhong Shen; Yuran Qiao; Mei Wen; Chunyuan Zhang (IEICE Electron. Express, 2018)

Scale-out Acceleration for 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. - Junzhong Shen; Deguang Wang; You Huang; Mei Wen; Chunyuan Zhang (DAC, 2019)

Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. - Junzhong Shen; Deguang Wang; You Huang; Mei Wen; Chunyuan Zhang (FPGA, 2019)

An Efficient Design Flow for Accelerating Complicated-connected CNNs on a Multi-FPGA Platform. - Deguang Wang; Junzhong Shen; Mei Wen; Chunyuan Zhang (ICPP, 2019)

Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs. - Deguang Wang; Junzhong Shen; Mei Wen; Chunyuan Zhang (ISCAS, 2019)

Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA. - Minjin Tang; Mei Wen; Junzhong Shen; Xiaolei Zhao; Chunyuan Zhang (DAC, 2020)

Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement. - Junzhong Shen; Mei Wen; Minjin Tang; Xiaolei Zhao; Chunyuan Zhang (FPGA, 2020)

Towards a Deep-Pipelined Architecture for Accelerating Deep GCN on a Multi-FPGA Platform. - Qixuan Cheng; Mei Wen; Junzhong Shen; Deguang Wang; Chunyuan Zhang (ICA3PP (1), 2020)

P4 to FPGA-A Fast Approach for Generating Efficient Network Processors. - Zhuang Cao; Huayou Su; Qianming Yang; Junzhong Shen; Mei Wen; Chunyuan Zhang (IEEE Access, 2020)

Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA. - Junzhong Shen; You Huang; Mei Wen; Chunyuan Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Embrace the Conflicts: Exploring the Integration of Single Port Memory in Systolic Array-based Accelerators. - Renyu Yang; Junzhong Shen; Mei Wen; Yasong Cao; Yuhang Li (HPCC/DSS/SmartCity/DependSys, 2021)

SAI: Self-Adjusting Incremental Quantile Estimation for Sparse Training of Neural Networks on Hardware Accelerators. - Jianchao Yang; Mei Wen; Minjin Tang; Junzhong Shen; Chunyuan Zhang (HPCC/DSS/SmartCity/DependSys, 2021)

MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications. - Yasong Cao; Mei Wen; Junzhong Shen; Sheng Liu 001; Zhi Wang; Minjin Tang; Yahao Fang; Jianchao Yang; Renyu Yang; Yuhan Kang; Jiawei Fei (HPCC/DSS/SmartCity/DependSys, 2022)

BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. - Jianchao Yang; Mei Wen; Junzhong Shen; Yasong Cao; Minjin Tang; Renyu Yang; Jiawei Fei; Chunyuan Zhang (ICCD, 2022)

Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. - Minjin Tang; Mei Wen; Yasong Cao; Junzhong Shen; Jianchao Yang; Jiawei Fei; Yang Guo 003; Sheng Liu 001 (ICPP, 2022)

S-SIM: A Simulator for Systolic Array-based DNN Accelerators with Tile Access Awareness. - Yuhang Li; Mei Wen; Renyu Yang; Junzhong Shen; Yasong Cao; Jianan Wang (ISCAS, 2022)

TILE-SIM: A Systematic Approach to Systolic Array-based Accelerator Evaluation. - Yuhang Li; Mei Wen; Jiawei Fei; Junzhong Shen; Yasong Cao (ISPASS, 2022)

BitShare: An Efficient Precision-Scalable Accelerator with Combining-Like-Terms GEMM. - Yasong Cao; Mei Wen; Junzhong Shen; Zhongxing Li (ASAP, 2024)

MACO: Exploring GEMM Acceleration on a Loosely-Coupled Multi-Core Processor. - Bingcai Sui; Junzhong Shen; Caixia Sun; Junhui Wang; Zhong Zheng; Wei Guo (DATE, 2024)

MAP-SIM: A Performance Model for Shared-Memory Heterogeneous Systems with Mapping Awareness. - Yuhang Li; Mei Wen; Junzhong Shen; Zhaoyun Chen; Yang Shi 008 (ICA3PP (1), 2024)

MSA2: An Efficient Sparsity-Aware Accelerator for Matrix Multiplication with Multi-core Systolic Arrays. - Minjin Tang; Mei Wen; Junzhong Shen; Jingkui Yang; Zeyu Xue; Zili Shao (ICA3PP (3), 2024)

Enhancing the PE Utilization for Multi-Precision Systolic Array via Optimizing Computation Latency. - Jing Feng; Mei Wen; Xin Ju 005; Junzhong Shen; Yang Guo 003 (ISCAS, 2024)

HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs. - Jianchao Yang; Mei Wen; Dong Chen 015; Zhaoyun Chen; Zeyu Xue; Yuhang Li; Junzhong Shen; Yang Shi 008 (MICRO, 2024)

ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core. - Yasong Cao; Mei Wen; Zhongdi Luo; Xin Ju 005; Haolan Huang; Junzhong Shen; Haiyan Chen (IEEE Trans. Very Large Scale Integr. Syst., 2024)

WinAcc: Window-based Acceleration of Neural Networks Using Block Floating Point. - Xin Ju 005; Jun He; Mei Wen; Jing Feng; Yasong Cao; Junzhong Shen; Zhaoyun Chen; Yang Shi 008 (DATE, 2025)

SparSynergy: Unlocking Flexible and Efficient DNN Acceleration Through Multi-Level Sparsity. - Jingkui Yang; Mei Wen; Junzhong Shen; Jianchao Yang; Yasong Cao; Jun He; Minjin Tang; Zhaoyun Chen; Yang Shi 008 (DATE, 2025)

CAMO: A High-Performance CIM-based Lightweight CNN Accelerator for Mobile Devices. - Xin Ju; Renyu Yang; Mei Wen; Junzhong Shen; Tianyu Wang 009; Zhaoyan Shen; Zili Shao; Bin Liang (ISCAS, 2025)

SPSA: Exploring Sparse-Packing Computation on Systolic Arrays From Scratch. - Minjin Tang; Mei Wen; Jianchao Yang; Zeyu Xue; Junzhong Shen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

ISOAcc: In-situ Shift Operation-based Accelerator For Efficient in-SRAM Multiplication. - Gaoyang Zhao; Junzhong Shen; Rongzhen Lin; Hua Li; Yaohua Wang (ACM Trans. Design Autom. Electr. Syst., 2025)

FAMS: A FrAmework of Memory-Centric Mapping for DNNs on Systolic Array Accelerators. - Hao Sun; Junzhong Shen; Tian Zhang; Zhongyi Tang; Changwu Zhang; Yuhang Li; Yang Shi 008; Hengzhu Liu (IEEE Trans. Very Large Scale Integr. Syst., 2025)