Test-Process Simulation with Neural Network Evaluation. - Juraj Povazanec; Jirí Kaderka; Vladislav Musil; Petr Simek (ESM, 1996)

Neural network based system for testing and diagnostics of analogue integrated circuits. - Jirí Kaderka; Vladislav Musil; Juraj Povazanec; Petr Simek (ICECS, 1996)

Fault and test-process modelling for integrated circuits. - Juraj Povazanec; Vladislav Musil (J. Syst. Archit., 1997)

A Useful Micropipeline Architecture to Implement DSP Algorithms. - Oliver Chiu-sing Choy; Tin-Chak Johnson Pang; Juraj Povazanec; Cheong-Fat Chan (EUROMICRO, 1998)

Asynchronous logic in bit-serial arithmetic. - Juraj Povazanec; Chiu-Sing Choy; Cheong-Fat Chan (ICECS, 1998)

Pipelined Dataflow Architecture of a Small Processor. - Juraj Povazanec; Oliver Chiu-sing Choy; Cheong-Fat Chan; Jan Butas; Yeu-qiu Zhang; Jing-Ling Yang; Tin-yan Tang (PDPTA, 1999)

A single chip terminal solution for high-end telephone applications. - Vinod Nair; Martin Erdmann; Shridhar Mubaraq Mishra; Juraj Povazanec; Amit Shaligram; Chun Feng Hu (CICC, 2001)

Asynchronous cross-pipelined multiplier. - Jan Butas; Chiu-Sing Choy; Juraj Povazanec; Cheong-Fat Chan (IEEE J. Solid State Circuits, 2001)

A New Control Circuit for Asynchronous Micropipelines. - Oliver Chiu-sing Choy; Jan Butas; Juraj Povazanec; Cheong-Fat Chan (IEEE Trans. Computers, 2001)

Integration of SRAM Redundancy into Production Test. - Jayasanker Jayabalan; Juraj Povazanec (ITC, 2002)