Device and circuit models of InAlN/GaN D- and dual-gate E-mode HEMTs for design and characterisation of monolithic NAND logic cell. - Ales Chvála; Lukás Nagy; Juraj Marek; Juraj Priesol; Daniel Donoval; Alexander Satka; Michal Blaho; Dagmar Gregusová; Ján Kuzmík (DTIS, 2018)

Neural Network for Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Gates. - Ales Chvála; Lukás Nagy; Juraj Marek; Juraj Priesol; Daniel Donoval; Alexander Satka (DTIS, 2019)

Perimeter Driven Transport in the p-GaN Gate as a Limiting Factor for Gate Reliability. - Steve Stoffels; Niels Posthuma; Stefaan Decoutere; Benoit Bakeroot; Andrea Natale Tallarico; Enrico Sangiorgi; Claudio Fiegna; J. Zheng; X. Ma; Matteo Borga; Elena Fabris; Matteo Meneghini; et al. (IRPS, 2019)

Device and Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Cells Comprising D- and E-Mode HEMTs. - Ales Chvála; Lukás Nagy; Juraj Marek; Juraj Priesol; Daniel Donoval; Alexander Satka; Michal Blaho; Dagmar Gregusová; Ján Kuzmík (J. Circuits Syst. Comput., 2019)

Automatic Detection and Counting of Defects from Cathodoluminescence Maps of GaN Layers. - Juraj Priesol; David Gellen; Alexander Satka (MECO, 2023)