Design Technology co-optimization for N10. - Julien Ryckaert; Praveen Raghavan; Rogier Baert; Marie Garcia Bardon; Mircea Dusa; Arindam Mallik; Sushil Sakhare; Boris Vandewalle; Piet Wambacq; Bharani Chava; Kris Croes; Morin Dehan; et al. (CICC, 2014)

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. - Trong Huynh Bao; Dmitry Yakimets; Julien Ryckaert; Ivan Ciofi; Rogier Baert; Anabela Veloso; Jürgen Bömmels; Nadine Collaert; Philippe Roussel; S. Demuynck; Praveen Raghavan; Abdelkarim Mercha; et al. (ESSDERC, 2014)

As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability. - Baojun Tang; Kris Croes; Yohan Barbarin; Yunqi Wang; Robin Degraeve; Yunlong Li; Maria Toledano-Luque; Thomas Kauerauf; Jürgen Bömmels; Zsolt Tökei; Ingrid De Wolf (Microelectron. Reliab., 2014)

Impact of process variability on BEOL TDDB lifetime model assessment. - Kris Croes; Deniz Kocaay; Ivan Ciofi; Jürgen Bömmels; Zsolt Tökei (IRPS, 2015)

Intrinsic reliability of local interconnects for N7 and beyond. - Kris Croes; Alicja Lesniewska; Chen Wu; Ivan Ciofi; Agnieszka Banczerowska; B. Briggs; S. Demuynck; Zsolt Tökei; Jürgen Bömmels; Yves Saad; W. Gao (IRPS, 2015)

Constant voltage electromigration for advanced BEOL copper interconnects. - Baojun Tang; Kris Croes; Nicolas Jourdan 002; Jürgen Bömmels; Zsolt Tökei; Ingrid De Wolf; Eric Wilcox; Timothy McMullen (IRPS, 2015)

Evaluation of via density and low-k Young's modulus influence on mechanical performance of advanced node multi-level Back-End-Of-Line. - Luka Kljucar; Mario Gonzalez; Ingrid De Wolf; Kristof Croes; Jürgen Bömmels; Zsolt Tökei (Microelectron. Reliab., 2016)

Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation. - Houman Zahedmanesh; Mario Gonzalez; Ivan Ciofi; Kristof Croes; Jürgen Bömmels; Zsolt Tökei (Microelectron. Reliab., 2016)

Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects. - Luka Kljucar; Mario Gonzalez; Kristof Croes; Ingrid De Wolf; Joke De Messemaeker; Gayle Murdoch; Philip Nolmans; Joeri De Vos; Jürgen Bömmels; Eric Beyne; Zsolt Tökei (Microelectron. Reliab., 2017)

Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow. - Edouard Giacomin; Jürgen Bömmels; Julien Ryckaert; Francky Catthoor; Pierre-Emmanuel Gaillardon (VLSI-SOC, 2020)

3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs. - Edouard Giacomin; Jürgen Bömmels; Julien Ryckaert; Francky Catthoor; Pierre-Emmanuel Gaillardon (VLSI-SoC (Selected Papers), 2020)

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. - Hans Mertens; M. Hosseini; Thomas Chiarella; D. Zhou; S. Wang; G. Mannaert; E. Dupuy; D. Radisic; Z. Tao; Yusuke Oniki; Andriy Hikavyy; R. Rosseel; et al. (VLSI Technology and Circuits, 2023)

Integration of a Stacked Contact MOL for Monolithic CFET. - Victor Vega-Gonzalez; D. Radisic; Bt Chan; S. Choudhury; S. Wang; A. Mingardi; Q. Toan Le; H. Decoster; Yusuke Oniki; P. Puttarame; Kevin Vandersmissen; J. P. Soulie; et al. (VLSI Technology and Circuits, 2023)

3D SRAM Macro Design in 3D Nanofabric Process Technology. - Dawit Burusie Abdi; Shairfe Muhammad Salahuddin; Jürgen Bömmels; Edouard Giacomin; Pieter Weckx; Julien Ryckaert; Geert Hellings; Francky Catthoor (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts. - Steven Demuynck; Victor Vega-Gonzalez; C. Toledo de Carvalho Cavalcante; L. Petersen Barbosa Lima; K. Stiers; C. Sheng; A. Vandooren; M. Hosseini; X. Zhou; Hans Mertens; Thomas Chiarella; Jürgen Bömmels; et al. (VLSI Technology and Circuits, 2024)