An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement. - Ren-Song Tsay; Jürgen Koehl (DAC, 1991)

Standard-cell-based design methodology for high-performance support chips. - Bernhard Kick; Ulrich Baur; Jürgen Koehl; Thomas Ludwig 004; Thomas Pflueger (IBM J. Res. Dev., 1997)

A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset. - Jürgen Koehl; Ulrich Baur; Thomas Ludwig 004; Bernhard Kick; Thomas Pflueger (DATE, 1998)

Analysis, reduction and avoidance of crosstalk on VLSI chips. - Tilmann Stöhr; Markus Alt; Asmus Hetzel; Jürgen Koehl (ISPD, 1998)

Platzierungsbasierte Logikoptimierung komplexer VLSI Chips. - Jürgen Koehl; Jürgen Schietke (MBMV, 2000)

Automatic Hierarchical Design: Fantasy or Reality? (Panel). - Rob A. Rutenbar; Olivier Coudert; Patrick Groeneveld; Jürgen Koehl; Scott Peterson; Vivek Raghavan; Naresh Soni (ICCAD, 2001)

IBM's 50 Million gate ASICs. - Jürgen Koehl; David E. Lackey; George W. Doerre (ASP-DAC, 2003)

Designing mega-ASICs in nanogate technologies. - David E. Lackey; Paul S. Zuchowski; Jürgen Koehl (DAC, 2003)

DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. - Markus Bühler; Jürgen Koehl; Jeanne Bickford; Jason Hibbeler; Ulf Schlichtmann; Ralf Sommer; Michael Pronath; Andreas Ripp (DATE, 2006)

Yield Improvement by Local Wiring Redundancy. - Jeanne Bickford; Jason Hibbeler; Markus Bühler; Jürgen Koehl; Dirk Müller 003; Sven Peyer; Christian Schulte 002 (ISQED, 2006)

Robust wiring networks for DfY considering timing constraints. - Philipp V. Panitz; Markus Olbrich; Erich Barke; Jürgen Koehl (ACM Great Lakes Symposium on VLSI, 2007)

Considering possible opens in non-tree topology wire delay calculation. - Philipp V. Panitz; Markus Olbrich; Erich Barke; Markus Bühler; Jürgen Koehl (ACM Great Lakes Symposium on VLSI, 2008)