PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. - Andreas Herrmann; Erich Barke; Mathias Silvant; Jürgen Schlöffel (PATMOS, 2000)

Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. - Ajoy Kumar Palit; Volker Meyer; Walter Anheier; Jürgen Schlöffel (DFT, 2004)

A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. - Ajoy Kumar Palit; Lei Wu; Kishore K. Duganapalli; Walter Anheier; Jürgen Schlöffel (Asian Test Symposium, 2005)

PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. - Junhao Shi; Görschwin Fey; Rolf Drechsler; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel (ISVLSI, 2005)

ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. - Ajoy Kumar Palit; Volker Meyer; Walter Anheier; Jürgen Schlöffel (VLSI Design, 2005)

Implementing a Scheme for External Deterministic Self-Test. - Abdul Wahid Hakmi; Hans-Joachim Wunderlich; Valentin Gherman; Michael Garbers; Jürgen Schlöffel (VTS, 2005)

Fault detection and diagnosis with parity trees for space compaction of test responses. - Harald P. E. Vranken; Sandeep Kumar Goel; Andreas Glowatz; Jürgen Schlöffel; Friedrich Hapke (DAC, 2006)

X-masking during logic BIST and its impact on defect coverage. - Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilia Polian; Bernd Becker 001; Jürgen Schlöffel; Friedrich Hapke; Michael Wittke (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Computation and Application of Absolute Dominators in Industrial Designs. - Rene Krenz-Baath; Andreas Glowatz; Jürgen Schlöffel (ETS, 2007)

Synthesis of irregular combinational functions with large don't care sets. - Valentin Gherman; Hans-Joachim Wunderlich; R. D. Mascarenhas; Jürgen Schlöffel; Michael Garbers (ACM Great Lakes Symposium on VLSI, 2007)

Experimental Studies on SAT-Based ATPG for Gate Delay Faults. - Stephan Eggersglüß; Daniel Tille; Görschwin Fey; Rolf Drechsler; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel (ISMVL, 2007)

Programmable deterministic Built-In Self-Test. - Abdul Wahid Hakmi; Hans-Joachim Wunderlich; Christian G. Zoellin; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel; Laurent Souef (ITC, 2007)

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. - Stephan Eggersglüß; Görschwin Fey; Rolf Drechsler; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel (MEMOCODE, 2007)

Deterministic logic BIST for transition fault testing. - Valentin Gherman; Hans-Joachim Wunderlich; Jürgen Schlöffel; Michael Garbers (IET Comput. Digit. Tech., 2007)

Resistive Bridging Fault Simulation of Industrial Circuits. - Piet Engelke; Ilia Polian; Jürgen Schlöffel; Bernd Becker 001 (DATE, 2008)

On Acceleration of SAT-Based ATPG for Industrial Designs. - Rolf Drechsler; Stephan Eggersglüß; Görschwin Fey; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel; Daniel Tille (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs. - Friedrich Hapke; Rene Krenz-Baath; Andreas Glowatz; Jürgen Schlöffel; Hamidreza Hashempour; Stefan Eichenberger; Camelia Hora; Dan Adolfsson (ITC, 2009)

Restrict Encoding for Mixed-Mode BIST. - Abdul Wahid Hakmi; Stefan Holst; Hans-Joachim Wunderlich; Jürgen Schlöffel; Friedrich Hapke; Andreas Glowatz (VTS, 2009)

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). - Rolf Drechsler; Stephan Eggersglüß; Görschwin Fey; Jürgen Schlöffel; Daniel Tille (it Inf. Technol., 2009)

SUPERB: Simulator utilizing parallel evaluation of resistive bridges. - Piet Engelke; Bernd Becker 001; Michel Renovell; Jürgen Schlöffel; Bettina Braitling; Ilia Polian (ACM Trans. Design Autom. Electr. Syst., 2009)

Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. - Daniel Tille; Stephan Eggersglüß; Rene Krenz-Baath; Jürgen Schlöffel; Rolf Drechsler (ETS, 2010)

Defect-oriented cell-internal testing. - Friedrich Hapke; Wilfried Redemund; Jürgen Schlöffel; Rene Krenz-Baath; Andreas Glowatz; Michael Wittke; Hamidreza Hashempour; Stefan Eichenberger (ITC, 2010)

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. - Stephan Eggersglüß; Görschwin Fey; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel; Rolf Drechsler (J. Electron. Test., 2010)

Cell-aware analysis for small-delay effects and production test results from different fault models. - Friedrich Hapke; Jürgen Schlöffel; Wilfried Redemund; Andreas Glowatz; Janusz Rajski; Michael Reese; J. Rearick; Jason Rivers (ITC, 2011)

Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates. - Friedrich Hapke; Jürgen Schlöffel (ETS, 2012)

Cell-aware Production test results from a 32-nm notebook processor. - Friedrich Hapke; Michael Reese; Jason Rivers; A. Over; V. Ravikumar; Wilfried Redemund; Andreas Glowatz; Jürgen Schlöffel; Janusz Rajski (ITC, 2012)

Cell-aware experiences in a high-quality automotive test suite. - Friedrich Hapke; Ralf Arnold; Matthias Beck; M. Baby; S. Straehle; J. F. Goncalves; A. Panait; R. Behr; Gwenolé Maugard; A. Prashanthi; Juergen Schloeffel; Wilfried Redemund; et al. (ETS, 2014)

2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. - Yassine Fkih; Pascal Vivet; Bruno Rouzeyre; Marie-Lise Flottes; Giorgio Di Natale; Juergen Schloeffel (ISVLSI, 2014)

Cell-Aware Test. - Friedrich Hapke; Wilfried Redemund; Andreas Glowatz; Janusz Rajski; Michael Reese; Marek Hustava; Martin Keim; Juergen Schloeffel; Anja Fast (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

3D DFT Challenges and Solutions. - Yassine Fkih; Pascal Vivet; Marie-Lise Flottes; Bruno Rouzeyre; Giorgio Di Natale; Juergen Schloeffel (ISVLSI, 2015)

IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system. - Jean Durupt; Pascal Vivet; Juergen Schloeffel (ETS, 2016)

A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Cristiano Santos; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Denis Dutoit; Fabien Clermidy; Séverine Cheramy; et al. (IEEE J. Solid State Circuits, 2017)