Providing network connectivity for small appliances: a functionally minimized embedded Web server. - Janne Riihijärvi; Petri Mähönen; Mika J. Saaranen; Jussi Roivainen; Juha-Pekka Soininen (IEEE Commun. Mag., 2001)

Configurable Memory Organisation for Communication Applications. - Juha-Pekka Soininen; Antti Pelkonen; Jussi Roivainen (DSD, 2002)

IP-Block Based Integration of Very High Performance WLAN Modem. - Jussi Roivainen; Jukka Rautio (DSD, 2004)

Clock-Gating in FPGAs: A Novel and Comparative Evaluation. - Yan Zhang; Jussi Roivainen; Aarne Mämmelä (DSD, 2006)

Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architectures. - Martti Forsell; Jussi Roivainen (PDPTA, 2008)

REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor. - Martti Forsell; Jussi Roivainen (ACSSC, 2014)

Prototyping the MBTAC Processor for the REPLICA CMP. - Martti Forsell; Jussi Roivainen; Ville Leppänen (IPDPS Workshops, 2014)

The REPLICA on-chip network. - Martti Forsell; Jussi Roivainen; Ville Leppänen (NORCAS, 2016)

Outline of a Thick Control Flow Architecture. - Martti Forsell; Jussi Roivainen; Ville Leppänen (SBAC-PAD (Workshops), 2016)

Supporting concurrent memory access in TCF-aware processor architectures. - Martti Forsell; Jussi Roivainen; Ville Leppänen; Jesper Larsson Träff (NORCAS, 2017)

Implementation of Multioperations in Thick Control Flow Processors. - Martti Forsell; Jussi Roivainen; Ville Leppänen; Jesper Larsson Träff (IPDPS Workshops, 2018)

Supporting concurrent memory access in TCF processor architectures. - Martti Forsell; Jussi Roivainen; Ville Leppänen; Jesper Larsson Träff (Microprocess. Microsystems, 2018)

REPLICA MBTAC: multithreaded dual-mode processor. - Martti Forsell; Jussi Roivainen; Ville Leppänen (J. Supercomput., 2018)

5G Radar: Scenarios, Numerology and Simulations. - Markku Kiviranta; Ilkka Moilanen; Jussi Roivainen (ICMCIS, 2019)

Optimizing Memory Access in TCF Processors with Compute-Update Operations. - Martti Forsell; Jussi Roivainen; Jesper Larsson Träff (IPDPS Workshops, 2020)

Performance and programmability comparison of the thick control flow architecture and current multicore processors. - Martti Forsell; Sara Nikula; Jussi Roivainen; Ville Leppänen; Jesper Larsson Träff (J. Supercomput., 2022)

Preliminary Performance and Memory Access Scalability Study of Thick Control Flow Processors. - Martti Forsell; Jussi Roivainen; Ville Leppänen; Jesper Larsson Träff (NorCAS, 2023)

Realizing multioperations and multiprefixes in Thick Control Flow processors. - Martti Forsell; Jussi Roivainen; Ville Leppänen; Jesper Larsson Träff (Microprocess. Microsystems, 2023)