Quality assurance in memory built-in self-test tools. - Albert Au; Artur Pogiel; Janusz Rajski; Piotr Sydow; Jerzy Tyszer; Justyna Zawada (DDECS, 2014)

Design for low test pattern counts. - Haluk Konuk; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Deepak Solanki; Jerzy Tyszer; Justyna Zawada (DAC, 2015)

Embedded deterministic test points for compact cell-aware tests. - Cesar Acero; Derek Feltham; Friedrich Hapke; Elham K. Moghaddam; Nilanjan Mukherjee 001; Vidya Neerkundar; Marek Patyra; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ITC, 2015)

On Test Points Enhancing Hardware Security. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ATS, 2016)

Test point insertion in hybrid test compression/LBIST architectures. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ITC, 2016)

On New Test Points for Compact Cell-Aware Tests. - Cesar Acero; Derek Feltham; Marek Patyra; Friedrich Hapke; Elham K. Moghaddam; Nilanjan Mukherjee 001; Vidya Neerkundar; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (IEEE Des. Test, 2016)

Full-scan LBIST with capture-per-cycle hybrid test points. - Sylwester Milewski; Nilanjan Mukherjee 001; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer; Justyna Zawada (ITC, 2017)

Embedded Deterministic Test Points. - Cesar Acero; Derek Feltham; Yingdi Liu; Elham K. Moghaddam; Nilanjan Mukherjee 001; Marek Patyra; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Very Large Scale Integr. Syst., 2017)

On New Class of Test Points and Their Applications. - Janusz Rajski; Jerzy Tyszer; Justyna Zawada (ITC, 2018)

Hardware Protection via Logic Locking Test Points. - Michael Chen; Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Logic BIST With Capture-Per-Clock Hybrid Test Points. - Elham K. Moghaddam; Nilanjan Mukherjee 001; Janusz Rajski; Jedrzej Solecki; Jerzy Tyszer; Justyna Zawada (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Test Challenges of Intel IA Cores. - Uri Shpiro; Khen Wee; Kun-Han Tsai; Justyna Zawada; Xijiang Lin (ITC, 2020)

Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. - Fong-Jyun Tsai; Chong-Siao Ye; Kuen-Jong Lee; Shi-Xuan Zheng; Yu Huang 005; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski; Chen Wang 014; Justyna Zawada (ITC, 2020)

Efficient Test Compression Configuration Selection. - Chong-Siao Ye; Shi-Xuan Zheng; Fong-Jyun Tsai; Chen Wang 014; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Justyna Zawada; Mark Kassab; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)