A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. - Dinesh Kushwaha; Aditya Sharma; Neha Gupta; Ritik Raj; Ashish Joshi; Jwalant Mishra; Rajat Kohli; Sandeep Miryala; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (ISCAS, 2022)

A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application. - Dinesh Kushwaha; Rajat Kohli; Jwalant Mishra; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (AICAS, 2023)

An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture. - Dinesh Kushwaha; Rajat Kohli; Jwalant Mishra; Jainendra Singh; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (LASCAS, 2024)

Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network. - Dinesh Kushwaha; Jaya Kumar Abotula; Rajat Kohli; Jwalant Mishra; Sudeb Dasgupta; Anand Bulusu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Robust Verification Methodology for Scan Chain in Memories. - Rajat Kohli; Umang Deep; Vaishnavi Holla; Jwalant Kumar Mishra (VLSID, 2025)