Checkpoints in irredundant two-level combinational circuits. - Jwu E. Chen; Chung-Len Lee 001; Wen-Zen Shen (J. Electron. Test., 1991)

Single-fault fault-collapsing analysis in sequential logic circuits. - Jwu E. Chen; Chung-Len Lee 001; Wen-Zen Shen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. - Hui Min Wang; Chung-Len Lee 001; Jwu E. Chen (ISMVL, 1992)

TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator. - Meng Chiy Lin; Jwu E. Chen; Chung-Len Lee 001 (EDAC-ETC-EUROASIC, 1994)

Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. - Wen Ching Wu; Chung-Len Lee 001; Jwu E. Chen; Won Yih Lin (EDAC-ETC-EUROASIC, 1994)

Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits. - Hui Min Wang; Chung-Len Lee 001; Jwu E. Chen (ISMVL, 1994)

Complete Test Set for Multiple-Valued Logic Networks. - Hui Min Wang; Chung-Len Lee 001; Jwu E. Chen (ISMVL, 1994)

Fanout fault analysis for digital logic circuits. - Jwu E. Chen; Chung-Len Lee 001; Wen-Zen Shen; Beyin Chen (Asian Test Symposium, 1995)

Identification of robust untestable path delay faults. - Wen Ching Wu; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 1995)

Factorization of Multi-Valued Logic Functions. - Hui Min Wang; Chung-Len Lee 001; Jwu E. Chen (ISMVL, 1995)

Identifying Untestable Faults in Sequential Circuits. - Hsing-Chung Liang; Chung-Len Lee 001; Jwu E. Chen (IEEE Des. Test Comput., 1995)

Yield Improvement by Test Error Cancellation. - Jwu E. Chen (Asian Test Symposium, 1996)

Invalid State Identification for Sequential Circuit Test Generation. - Hsing-Chung Liang; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 1996)

Fault diagnosis of odd-even sorting networks. - Chih Wei Hu; Chung-Len Lee 001; Wen Ching Wu; Jwu E. Chen (Asian Test Symposium, 1997)

Functional test pattern generation for CMOS operational amplifier. - Soon-Jyh Chang; Chung-Len Lee 001; Jwu E. Chen (VTS, 1997)

Identifying invalid states for sequential circuit test generation. - Hsing-Chung Liang; Chung-Len Lee 001; Jwu E. Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Maximization of power dissipation under random excitation for burn-in testing. - Kuo-Chan Huang; Chung-Len Lee 001; Jwu E. Chen (ITC, 1998)

Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. - Hsing-Chung Liang; Chung-Len Lee 001; Jwu E. Chen (VTS, 1998)

A Two-Phase Fault Simulation Scheme for Sequential Circuits. - Wen Ching Wu; Chung-Len Lee 001; Jwu E. Chen (J. Inf. Sci. Eng., 1998)

A DFT for semi-DC fault diagnosis for switched-capacitor circuits. - Sheng-Jer Kuo; Chung Len Lee 001; Soon-Jyh Chang; Jwu E. Chen (ETW, 1999)

A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model. - Kuo-Chan Huang; Chung-Len Lee 001; Jwu E. Chen (J. Inf. Sci. Eng., 1999)

A methodology for fault model development for hierarchical linear systems. - Yin-Chao Huang; Chung-Len Lee 001; Jun-Weir Lin; Jwu E. Chen; Chauchin Su (Asian Test Symposium, 2000)

A case study of failure analysis and guardband determination for a 64M-bit DRAM. - Chin-Te Kao; Sam Wu; Jwu E. Chen (Asian Test Symposium, 2000)

Is IDDQ testing not applicable for deep submicron VLSI in year 2011? - Chih-Wen Lu; Chauchin Su; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 2000)

Oscillation Ring Delay Test for High Performance Microprocessors. - Wen Ching Wu; Chung-Len Lee 001; Ming Shae Wu; Jwu E. Chen; Magdy S. Abadir (J. Electron. Test., 2000)

A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. - Yeong-Jar Chang; Chung-Len Lee 001; Jwu E. Chen; Chauchin Su (J. Inf. Sci. Eng., 2000)

Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing. - Mill-Jer Wang; R.-L. Jiang; J.-W. Hsia; Chih-Hu Wang; Jwu E. Chen (Asian Test Symposium, 2001)

Fault Diagnosis for Linear Analog Circuits. - Jun-Weir Lin; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (J. Electron. Test., 2001)

A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal. - Ming Shae Wu; Chung-Len Lee 001; Chi Peng Chang; Jwu E. Chen (Asian Test Symposium, 2002)

An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. - Jun-Weir Lin; Chung-Len Lee 001; Jwu E. Chen (DATE, 2002)

Structural Fault Based Specification Reduction for Testing Analog Circuits. - Soon-Jyh Chang; Chung-Len Lee 001; Jwu E. Chen (J. Electron. Test., 2002)

Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. - Soon-Jyh Chang; Chung-Len Lee 001; Jwu E. Chen (J. Inf. Sci. Eng., 2003)

A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC. - Guan-Xun Chen; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 2004)

A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (Asian Test Symposium, 2004)

Oscillation ring based interconnect test scheme for SOC. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (ASP-DAC, 2005)

Finite State Machine Synthesis for At-Speed Oscillation Testability. - Katherine Shu-Min Li; Chung-Len Lee 001; Tagin Jiang; Chauchin Su; Jwu E. Chen (Asian Test Symposium, 2005)

A Scan Matrix Design for Low Power Scan-Based Test. - Shih Ping Lin 001; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 2005)

Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. - Shih Ping Lin 001; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 2005)

A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. - Shih Ping Lin 001; Chung-Len Lee 001; Jwu E. Chen; Ji-Jan Chen; Kun-Lun Luo; Wen Ching Wu (ITC, 2006)

IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. - Katherine Shu-Min Li; Chauchin Su; Yao-Wen Chang; Chung-Len Lee 001; Jwu E. Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (J. Electron. Test., 2007)

Multilevel Full-Chip Routing With Testability and Yield Enhancement. - Katherine Shu-Min Li; Yao-Wen Chang; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Repeated Testing Applications for Improving the IC Test Quality to Achieve Zero Defect Product Requirements. - Chung-Huang Yeh; Jwu E. Chen (J. Electron. Test., 2019)

Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. - Ken Chau-Cheung Cheng; Katherine Shu-Min Li; Andrew Yi-Ann Huang; Ji-Wei Li; Leon Li-Yang Chen; Nova Cheng-Yen Tsai; Sying-Jyan Wang; Chen-Shiun Lee; Leon Chou; Peter Yi-Yu Liao; Hsing-Chung Liang; Jwu E. Chen (DATE, 2020)

The Decision Mechanism Uses the Multiple-Tests Scheme to Improve Test Yield in IC Testing. - Chung-Huang Yeh; Jwu E. Chen (ITC-Asia, 2020)

Innovative Practice on Wafer Test Innovations. - Dyi-Chung Hu; Hirohito Hashimoto; Li-Fong Tseng; Ken Chau-Cheung Cheng; Katherine Shu-Min Li; Sying-Jyan Wang; Sean Y.-S. Chen; Jwu E. Chen; Clark Liu; Andrew Yi-Ann Huang (VTS, 2020)

Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. - Katherine Shu-Min Li; Leon Li-Yang Chen; Ken Chau-Cheung Cheng; Peter Yi-Yu Liao; Sying-Jyan Wang; Andrew Yi-Ann Huang; Nova Cheng-Yen Tsai; Leon Chou; Gus Chang-Hung Han; Jwu E. Chen; Hsing-Chung Liang; Chun-Lung Hsu (ETS, 2021)

Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. - Leon Li-Yang Chen; Katherine Shu-Min Li; Xu-Hao Jiang; Sying-Jyan Wang; Andrew Yi-Ann Huang; Jwu E. Chen; Hsing-Chung Liang; Chun-Lung Hsu (ITC, 2021)

Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect. - Chung-Huang Yeh; Jwu E. Chen (Sensors, 2022)

Multiple Retest Systems for Screening High-Quality Chips. - Chung-Huang Yeh; Jwu E. Chen (J. Electron. Test., 2023)

Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments. - Chung-Huang Yeh; Jwu E. Chen (IEEE Des. Test, 2023)

Prediction of the Test Yield of Future Integrated Circuits Through the Deductive Estimation Method. - Chung-Huang Yeh; Jwu E. Chen (J. Circuits Syst. Comput., 2023)