A New 1T DRAM Cell With Enhanced Floating Body Ef. - Jyi-Tsong Lin; Mike Chang (MTDT, 2006)

Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI. - Jyi-Tsong Lin; Yi-Chuen Eng; Tai-Yi Lee; Kao-Cheng Lin (VLSI Design, 2007)

Analysis of Block Oxide Height Variations for a 40nm Gate Length bFDSOI-FET. - Jyi-Tsong Lin; Yi-Chuen Eng (J. Comput., 2008)

A unipolar-CMOS with recessed source/drain load. - Jyi-Tsong Lin; Hsuan-Hsu Chen; Kuan-Yu Lu; Chih-Hung Sun; Tung-Yen Lai; Fu-Liang Yang (ASICON, 2011)

Using GIDL mechanism for low-power consumption and data retention time improvement in a double-gate nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body structure. - Wei-Han Lee; Jyi-Tsong Lin; Yu-Chun Wang; Po-Hsieh Lin; Chien-Chia Lai; Yong-Huang Lin; Tin-Chun Chang (ASICON, 2015)

Threshold-voltage variability analysis and modeling for junctionless double-gate transistors. - Chun-Yu Chen; Jyi-Tsong Lin; Meng-Hsueh Chiang (Microelectron. Reliab., 2017)

Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory. - Md. Hasan Raza Ansari; Nupur Navlakha; Jyi-Tsong Lin; Abhinav Kranti (VLSID, 2018)

Performances Improvement of Tunneling Field-Effect Transistors' with the Advanced Double-Gate PN Construction. - Yu-Jen Chen; Jyi-Tsong Lin (ICCE-TW, 2020)

Steeper Subthreshold Swing Attained in Ge-Source Inductive Tunneling FET via Epitaxial Tunnel Layer for Suppressed Point Tunneling. - Yen-Chen Chang; Wei-Heng Tai; Jyi-Tsong Lin (ASICON, 2023)

A Simple New Line-Tunneling iTFET with Overlapping Between Gate and Source Contact. - Jyi-Tsong Lin; Kuan-Pin Lin (ASICON, 2023)

An iTFET with Control Gate for Low Power Applications in RF and Digital Circuits. - Ho-Hin Tse; Zheng-Hong Zhong; Jyi-Tsong Lin (ASICON, 2023)