A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop. - Uday Kiran Naidu Ekkurthi; Venkatesh Dasari; Jyoshnavi Akiri; Chua-Chin Wang (ISCAS, 2021)

A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology. - Jyoshnavi Akiri; Lean Karlo S. Tolentino; Lung-Jieh Yang; Balasubramanian Esakki; Sivaperumal Sampath; Chua-Chin Wang (APCCAS, 2022)