High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR-XNOR Cell. - Jyoti Kandpal; Abhishek Tomar; Mayur Agarwal; Kamal Kumar Sharma (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications. - Jyoti Kandpal; Abhishek Tomar; Mayur Agarwal (Microelectron. J., 2021)

A variation resilient keeper design for high performance domino logic applications. - Jyoti Kandpal; Tika Ram Pokhrel; Shalu Saini; Alak Majumder (Integr., 2023)

Design of a Bandgap Voltage Reference Circuit in 90 nm CMOS Process. - Upal Barua Joy; Arindom Chakraborty; Jyoti Kandpal; Md. Shahbaz Hussain (ICCCNT, 2024)