A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access. - Venkatesh Mani Tripathi; Sandeep Mishra; Jyotishman Saikia; Anup Dandapat (VLSID, 2017)

A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme. - Sandeep Mishra; Telajala Venkata Mahendra; Jyotishman Saikia; Anup Dandapat (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM. - Jyotishman Saikia; Shihui Yin; Zhewei Jiang; Mingoo Seok; Jae-sun Seo (ISLPED, 2019)

Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design. - Jyotishman Saikia; Shihui Yin; Sai Kiran Cherupally; Bo Zhang 105; Jian Meng; Mingoo Seok; Jae-Sun Seo (DATE, 2021)

PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. - Shihui Yin; Bo Zhang 105; Minkyu Kim 001; Jyotishman Saikia; Soonwan Kwon; Sungmeen Myung; Hyunsoo Kim; Sang Joon Kim; Mingoo Seok; Jae-sun Seo (VLSI Circuits, 2021)

A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks. - Bo Zhang 105; Jyotishman Saikia; Jian Meng; Dewei Wang; Soonwan Kwon; Sungmeen Myung; Hyunsoo Kim; Sang Joon Kim; Jae-sun Seo; Mingoo Seok (CICC, 2022)

A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification. - Shreyas Kolala Venkataramanaiah; Jian Meng; Han-Sok Suh; Injune Yeo; Jyotishman Saikia; Sai Kiran Cherupally; Yichi Zhang 006; Zhiru Zhang; Jae-sun Seo (ESSCIRC, 2022)

FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro. - Jyotishman Saikia; Amitesh Sridharan; Injune Yeo; Shreyas K. Venkataramanaiah; Deliang Fan; Jae-Sun Seo (ESSCIRC, 2023)

A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity. - Shreyas Kolala Venkataramanaiah; Jian Meng; Han-Sok Suh; Injune Yeo; Jyotishman Saikia; Sai Kiran Cherupally; Yichi Zhang 006; Zhiru Zhang; Jae-Sun Seo (IEEE J. Solid State Circuits, 2023)

PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference. - Bo Zhang 105; Shihui Yin; Minkyu Kim 001; Jyotishman Saikia; Soonwan Kwon; Sungmeen Myung; Hyunsoo Kim; Sang Joon Kim; Jae-Sun Seo; Mingoo Seok (IEEE J. Solid State Circuits, 2023)

MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks. - Bo Zhang 105; Jyotishman Saikia; Jian Meng; Dewei Wang; Soonwan Kwon; Sungmeen Myung; Hyunsoo Kim; Sang Joon Kim; Jae-Sun Seo; Mingoo Seok (IEEE J. Solid State Circuits, 2024)