Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. - Shao-Cheng Wang; Geng-Cing Lin; Yi-Wei Lin; Ming-Chien Tsai; Yi-Wei Chiu; Shyh-Jye Jou; Ching-Te Chuang; Nan-Chun Lien; Wei-Chiang Shih; Kuen-Di Lee; Jyun-Kai Chu (APCCAS, 2012)

An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. - Geng-Cing Lin; Shao-Cheng Wang; Yi-Wei Lin; Ming-Chien Tsai; Ching-Te Chuang; Shyh-Jye Jou; Nan-Chun Lien; Wei-Chiang Shih; Kuen-Di Lee; Jyun-Kai Chu (ISCAS, 2012)