Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell. - Pulkit Sharma; R. Anusha; K. Bharath; Jasmine Kaur Gulati; Preet K. Walia; Sumit Jagdish Darak (VDAT, 2016)

Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology. - Harsh Rawat; K. Bharath; Alexander Fell (SoCC, 2017)

Designing Low Cost Secured DSP Core using Steganography and PSO for CE systems. - Aditya Anshul; K. Bharath; Anirban Sengupta (iSES, 2022)

Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores. - Mahendra Rathor; Aditya Anshul; K. Bharath; Rahul Chaurasia; Anirban Sengupta (Comput. Electr. Eng., 2023)

Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs. - Anirban Sengupta; Rahul Chaurasia; K. Bharath (Comput. Electr. Eng., 2023)