A parallel architecture for recursive least square identification. - K. Hashimoto; H. Kimura (ICASSP, 1986)

Consideration of poly-Si loaded cell capacity limits for low-power and high-speed SRAMs. - Hideo Kato; Katsuhiko Sato; Masataka Matsui; H. Shibata; K. Hashimoto; Takayuki Ootani; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1992)

SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober. - Hideo Kato; Masataka Matsui; Katsuhiko Sato; H. Shibata; K. Hashimoto; Takayuki Ootani; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1997)

An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm. - Masayuki Miyama; Osamu Tooyama; N. Takamatsu; T. Kodake; K. Nakamura; A. Kato; Junichi Miyakoshi; K. Hashimoto; Shigenobu Komatsu; M. Yagi; Masao Morimoto; Kazuo Taki; et al. (CICC, 2002)