Fault-tolerant self-organizing map implemented by wafer-scale integration. - Moritoshi Yasunaga; I. Hachiya; K. Moki; Jung Hwan Kim (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Extending the Application of a Neural Network for Failure Analysis of Electronic Circuit Boards. - H. Tabuchi; T. Yamada; M. Usami; M. Nagao; K. Moki; T. Ochiai; M. Kawai (IIA/SOCO, 1999)