Low Power Reversible Parallel Binary Adder/Subtractor - H. G. Rangaraju; U. Venugopal; K. N. Muralidhara; K. B. Raja (CoRR, 2010)

Design of Efficient Reversible Multiplier. - H. G. Rangaraju; Aakash Babu Suresh; K. N. Muralidhara (ACITY (3), 2012)