Delay and peak power minimization for on-chip buses using temporal redundancy. - K. Najeeb; Vishal Gupta; V. Kamakoti 001; Madhu Mutyam (ACM Great Lakes Symposium on VLSI, 2006)

Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. - K. Najeeb; Vishal Gupta; V. Kamakoti 001; Madhu Mutyam (J. Low Power Electron., 2006)

Controllability-driven Power Virus Generation for Digital Circuits. - K. Najeeb; Karthik Gururaj; V. Kamakoti 001; Vivekananda M. Vedula (VLSI Design, 2007)

Power Virus Generation Using Behavioral Models of Circuits. - K. Najeeb; Vishnu Vardhan Reddy Konda; Siva Kumar Sastry Hari; V. Kamakoti 001; Vivekananda M. Vedula (VTS, 2007)

Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits. - K. Najeeb; Karthik Gururaj; V. Kamakoti 001; Vivekananda M. Vedula (J. Low Power Electron., 2007)