Simplified algorithms based on Haar transforms for signal recognition in protective relays. - D. B. Fakruddin; K. Parthasarathy (Proc. IEEE, 1985)

On the direct parallel solution of systems of linear equations: New algorithms and systolic structures. - M. K. Sridhar; R. Srinath; K. Parthasarathy (Inf. Sci., 1987)

Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. - Debabrata Ghosh; S. K. Nandy 001; P. Sadayappan; K. Parthasarathy (DAC, 1993)

NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. - Debabrata Ghosh; S. K. Nandy 001; K. Parthasarathy; V. Visvanathan (VLSI Design, 1993)

TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 –> 2 Compressor. - Debabrata Ghosh; S. K. Nandy 001; K. Parthasarathy (VLSI Design, 1994)

A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. - G. N. Rathna; S. K. Nandy 001; K. Parthasarathy (VLSI Design, 1994)

Phase space frames and frame operators. - T. C. Easwaran Nambudiri; K. Parthasarathy (Int. J. Wavelets Multiresolution Inf. Process., 2014)