Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. - K. R. Shesha Shayee; Joonseok Park; Pedro C. Diniz (FPL, 2003)

Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. - Joonseok Park; Pedro C. Diniz; K. R. Shesha Shayee (IEEE Trans. Computers, 2004)