0.18um CMOS Technology in Implementation of S Box and a Modified S Box. - K. Rahimunnisa; K. Rajeshkumar; S. Suresh Kumar (WiMo/CoNeCo, 2011)

Efficient Techniques for the Implementation of AES SubByte and MixColumn Transformations. - K. Rahimunnisa; M. Priya Zach; S. Suresh Kumar; J. Jayakumar (ACITY (1), 2012)

PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC. - K. Rahimunnisa; P. Karthigaikumar; N. Anitha Christy; S. Suresh Kumar; J. Jayakumar (Central Eur. J. Comput. Sci., 2013)

FPGA implementation of AES algorithm for high throughput using folded parallel architecture. - K. Rahimunnisa; P. Karthigaikumar; Soumiya Rasheed; J. Jayakumar; S. Suresh Kumar (Secur. Commun. Networks, 2014)

A Hybrid Deep Learning Model for Real Time Hand Gestures Recognition. - Gnanapriya Sampath; K. Rahimunnisa (Intell. Autom. Soft Comput., 2023)

Intelligent maternal-fetal healthcare monitoring and abnormality detection using deep belief networks optimized by bacterial foraging algorithm. - K. Nandini; K. Rahimunnisa (Biomed. Signal Process. Control., 2025)