Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization. - N. N. Mojumder; Seung Chul Song; K. Rim; J. Xu; Joseph Wang; J. Zhu; Milena Vratonjic; K. Lin; Martin Saint-Laurent; Paul Bassett; Geoffrey Yeap (VLSIC, 2015)

Holistic technology optimization and key enablers for 7nm mobile SoC. - Seung Chul Song; J. Xu; N. N. Mojumder; K. Rim; D. Yang; Jerry Bao; J. Zhu; Joseph Wang; Mustafa Badaroglu; V. Machkaoutsan; Praneeth Narayanasetti; B. Bucki; et al. (VLSIC, 2015)

Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes. - Seung Chul Song; J. Xu; D. Yang; K. Rim; P. Feng; Jerry Bao; J. Zhu; Joseph Wang; G. Nallapati; Mustafa Badaroglu; Praneeth Narayanasetti; B. Bucki; et al. (VLSI Circuits, 2016)

Comprehensive Feasibility Study of Single FIN Transistors for Scaling Both Switching Energy and Device Footprint. - H. Fukutome; K. Suh; W. Kim; Y. Moriyama; S. Kang; B. Eom; J. Kim; C. Yoon; W. Kwon; Y. Chung; Y. Nam; Y. Kim; et al. (VLSI Technology and Circuits, 2022)

Device Design and Reliability of GAA MBCFET. - M. Kang; M. Chang; Y. Park; C. Noh; S. H. Hong; B. Park; Y. H. Park; Y. C. Jung; W. S. Lim; G. H. Kim; Y. Lee; H. Yang; et al. (IRPS, 2024)

Demonstration of Logic-Block Performance-Power-Area Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2 nm Node. - H. Fukutome; J. Kim; Joonghan Shin; J. Kim; Youngsoo Lee; S. Chae; B. Eom; Y. S. Nam; Minseong Lee; Sanghyun Ha; E. G. Chung; Sung-Hoon Lee; et al. (CICC, 2025)