Artificial neural networks as building blocks of mixed signal FPGA. - R. Manjunath; K. S. Gurumurthy (FPT, 2003)

Load Balancing in Multi ECU Configuration. - Rajeshwari Hegde; K. S. Gurumurthy (ARTCom, 2009)

Load Balancing towards ECU Integration. - Rajeshwari Hegde; K. S. Gurumurthy (ARTCom, 2009)

Moving From Binary Towards Multi-valued logic. - K. S. Vasundara Patel; K. S. Gurumurthy (CDES, 2009)

Arithmetic Operations in Multi-Valued Logic - K. S. Vasundara Patel; K. S. Gurumurthy (CoRR, 2010)

Sub Band Speech Analysis Using Gammatone Filter Banks and Optimal Pitch Extraction Methods for Each Sub Band Using Average Magnitude Difference Function (AMDF) for LPC Speech Coders in Noisy Environments. - Suma S. A.; K. S. Gurumurthy (J. Next Gener. Inf. Technol., 2010)

New Improved Echo Canceller Based on Normalized LMS Adaptive Filter for Single Talk and Double Talk Detection, Subband Echo Cancellation, Acoustic Echo Cancellation. - Suma S. A.; K. S. Gurumurthy (J. Next Gener. Inf. Technol., 2010)

Design of High Performance Quaternary Adders. - K. S. Vasundara Patel; K. S. Gurumurthy (ISMVL, 2011)

Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips. - R. Jayagowri; K. S. Gurumurthy (VDAT, 2012)

Deploying Health Monitoring ECU Towards Enhancing the Performance of In-Vehicle Network - Geetishree Mishra; Rajeshwari Hegde; K. S. Gurumurthy (CoRR, 2012)

Instruction Level Power Analysis for Low Power VLSI Applications. - Prashant V. Joshi; N. Prameela Kumari; K. S. Gurumurthy (ICETET, 2013)

Realization of Basic Gates Using Universal Logic Blocks in Quantum Dot Cellular Automata. - N. Prameela Kumari; Prashant V. Joshi; K. S. Gurumurthy (ICETET, 2013)