Moving From Binary Towards Multi-valued logic. - K. S. Vasundara Patel; K. S. Gurumurthy (CDES, 2009)

Arithmetic Operations in Multi-Valued Logic - K. S. Vasundara Patel; K. S. Gurumurthy (CoRR, 2010)

Design of High Performance Quaternary Adders. - K. S. Vasundara Patel; K. S. Gurumurthy (ISMVL, 2011)

Design and Complexity Analysis of Reed Solomon Code Algorithm for Advanced RAID System in Quaternary Domain. - Varun Vasudevan; Vinay Sheshadri; Sivarama Krishnan R.; K. S. Vasundara Patel (ISVLSI, 2011)

Modeling of Sigma-Delta ADC with High Resolution Decimation Filter. - G. N. Sowmya; K. S. Vasundara Patel; Rajani Rao (SPIT, 2012)

Study of LDPC decoders with quadratic residue sequence for communication system. - A. Rajagopal; K. Karibasappa; K. S. Vasundara Patel (Int. J. Inf. Comput. Secur., 2020)

Hardware implementation of a modified SSD LDPC decoder. - A. Rajagopal; K. Karibasappa; K. S. Vasundara Patel (Int. J. Comput. Aided Eng. Technol., 2021)