Fuzzy Distance Functions for Motion Planning. - K. Sridharan 001; Harry E. Stephanou (ICTAI, 1992)

On Computing a Distance Measure for Path Planning. - K. Sridharan 001; Harry E. Stephanou; S. Sathiya Keerthi (ICRA (1), 1993)

Algorithms for Rapid Computation of Some Distance Functions Between Objects for Path Planning. - K. Sridharan 001; Harry E. Stephanou (ICRA, 1994)

Distance Measures on Intersecting Objects and Their Applications. - K. Sridharan 001; Harry E. Stephanou; K. C. Craig; S. Sathiya Keerthi (Inf. Process. Lett., 1994)

Computation of penetration measures for convex polygons and polyhedra for graphics applications. - K. Sridharan 001 (HiPC, 1998)

A Parallel Algorithm to Construct Voronoi Diagram and Its VLSI Architecture. - N. Sudha; Sukumar Nandi; K. Sridharan 001 (ICRA, 1999)

Fuzzy distances for proximity characterization under uncertainty. - K. Sridharan 001; Harry E. Stephanou (Fuzzy Sets Syst., 1999)

Computing two penetration measures for curved 2D objects. - K. Sridharan 001 (Inf. Process. Lett., 1999)

Teaching computer graphics and robotics using symbolic computation software. - K. Sridharan 001 (Comput. Appl. Eng. Educ., 2000)

Computation of a penetration measure between 3D convex polyhedral objects for collision detection. - K. Sridharan 001; S. Sathiya Keerthi (J. Field Robotics, 2001)

Efficient computation of a measure of depth between convex objects for graphics applications. - K. Sridharan 001 (Comput. Graph., 2002)

The design and development of a web-based data acquisition system. - B. Rajesh Kumar; K. Sridharan 001; K. Srinivasan 003 (IEEE Trans. Instrum. Meas., 2002)

An Efficient Algorithm to Construct Reduced Visibility Graph and Its FPGA Implementation. - T. K. Priya; K. Sridharan 001 (VLSI Design, 2004)

A parallel algorithm for constructing reduced visibility graph and its FPGA implementation. - K. Sridharan 001; T. K. Priya (J. Syst. Archit., 2004)

A course on web languages and web-based applications. - K. Sridharan 001 (IEEE Trans. Educ., 2004)

Hardware-efficient schemes for logarithmic approximation and binary search with application to visibility graph construction. - Siew Kei Lam; K. Sridharan 001; Thambipillai Srikanthan (IEEE Trans. Ind. Electron., 2004)

A high-speed VLSI design and ASIC implementation for constructing Euclidean distance-based discrete Voronoi diagram. - Natarajan Sudha; K. Sridharan 001 (IEEE Trans. Robotics Autom., 2004)

VLSI-efficient schemes for high-speed construction of tangent graph. - Siew Kei Lam; K. Sridharan 001; Thambipillai Srikanthan (Robotics Auton. Syst., 2005)

The Design of a Hardware Accelerator for Real-Time Complete Visibility Graph Construction and Efficient FPGA Implementation. - K. Sridharan 001; T. K. Priya (IEEE Trans. Ind. Electron., 2005)

A hardware-efficient scheme and FPGA realization for computation of single pair shortest path for a mobile automaton. - T. K. Priya; P. Rajesh Kumar; K. Sridharan 001 (Microprocess. Microsystems, 2006)

A parallel algorithm, architecture and FPGA realization for high speed determination of the complete visibility graph for convex objects. - T. K. Priya; K. Sridharan 001 (Microprocess. Microsystems, 2006)

A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment. - P. Rajesh Kumar; K. Sridharan 001; S. Srinivasan 001 (Parallel Comput., 2006)

A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations. - K. Sridharan 001; T. K. Priya (IEEE Trans. Ind. Electron., 2007)

VLSI-Efficient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment. - P. Rajesh Kumar; K. Sridharan 001 (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Hardware-Efficient Prediction-Correction-Based Generalized-Voronoi-Diagram Construction and FPGA Implementation. - Leena Vachhani; K. Sridharan 001 (IEEE Trans. Ind. Electron., 2008)

Robotic Exploration and Landmark Determination: Hardware-Efficient Algorithms and FPGA Implementations. - K. Sridharan 001; Panakala Rajesh Kumar (Springer, 2008)

50 Years of CORDIC: Algorithms, Architectures, and Applications. - Pramod Kumar Meher; Javier Valls; Tso-Bing Juang; K. Sridharan 001; Koushik Maharatna (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation. - Leena Vachhani; K. Sridharan 001; Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Efficient FPGA Realization of CORDIC With Application to Robotic Exploration. - Leena Vachhani; K. Sridharan 001; Pramod Kumar Meher (IEEE Trans. Ind. Electron., 2009)

Robotic mapping with simple sensing and processing hardware - Algorithm and architecture. - Leena Vachhani; K. Sridharan 001 (ICARCV, 2010)

Efficient VLSI Architectures for the Hadamard Transform Based on Offset-Binary Coding and ROM Decomposition. - B. Sandeep Kumar; Vikram Pudi; K. Sridharan 001 (ISVLSI, 2011)

Efficient Design of a Hybrid Adder in Quantum-Dot Cellular Automata. - Vikram Pudi; K. Sridharan 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

New Decomposition Theorems on Majority Logic for Low-Delay Adder Designs in Quantum Dot Cellular Automata. - Vikram Pudi; K. Sridharan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A pipelined architecture for motion tracking on a multicore environment. - Natarajan Sudha; K. Sridharan 001; Dan Wilkinson (ISIC, 2014)

Very large-scale integration architecture for video stabilisation and implementation on a field programmable gate array-based autonomous vehicle. - Tahiyah Nou Shene; Vikramkumar Pudi; K. Sridharan 001; Vineetha Thomas; J. Arthi (IET Comput. Vis., 2015)

A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata. - Vikramkumar Pudi; K. Sridharan 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Design of Arithmetic Circuits in Quantum Dot Cellular Automata Nanotechnology - K. Sridharan 001; Vikram Pudi (Springer, 2015)

Low-Complexity Multiternary Digit Multiplier Design in CNTFET Technology. - Bodapati Srinivasu; K. Sridharan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Real-Time SURF-Based Video Stabilization System for an FPGA-Driven Mobile Robot. - Tahiyah Nou Shene; K. Sridharan 001; N. Sudha (IEEE Trans. Ind. Electron., 2016)

Carbon nanotube FET-based low-delay and low-power multi-digit adder designs. - Bodapati Srinivasu; K. Sridharan 001 (IET Circuits Devices Syst., 2017)

Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity. - Vikramkumar Pudi; K. Sridharan 001; Fabrizio Lombardi (IEEE Trans. Computers, 2017)

A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies. - B. Srinivasu; K. Sridharan 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Transistor-Level Probabilistic Approach for Reliability Analysis of Arithmetic Circuits With Applications to Emerging Technologies. - Bodapati Srinivasu; K. Sridharan 001 (IEEE Trans. Reliab., 2017)

Hardware-Efficient Velocity Estimation of Dynamic Obstacles Based on a Novel Radix-4 CORDIC and FPGA Implementation. - Yashrajsinh Parmar; K. Sridharan 001 (IECON, 2018)

Time Optimal Rendezvous for Multi-Agent Systems Amidst Obstacles - Theory and Experiments. - Bhaskar Vundurthy; K. Sridharan 001 (IECON, 2018)

Precomputation-based radix-4 CORDIC for approximate rotations and Hough transform. - Yashrajsinh Parmar; Krishnamurthy Sridharan (IET Circuits Devices Syst., 2018)

Analysing interactions between a trio of differential drive robots via a differential game formulation. - Sharad Kumar Singh; Puduru Viswanadha Reddy; K. Sridharan 001 (ACC, 2019)

Multiagent Gathering With Collision Avoidance and a Minimax Distance Criterion - Efficient Algorithms and Hardware Realization. - Bhaskar Vundurthy; K. Sridharan 001 (IEEE Trans. Ind. Informatics, 2019)

Interval Analysis Technique for Versatile and Parallel Multi-Agent Collision Detection and Avoidance. - Pranjal Vyas; Leena Vachhani; K. Sridharan 001 (J. Intell. Robotic Syst., 2020)

A Resource-Efficient Multiplierless Systolic Array Architecture for Convolutions in Deep Networks. - Yashrajsinh Parmar; K. Sridharan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Protecting an Autonomous Delivery Agent Against a Vision-Guided Adversary: Algorithms and Experimental Results. - Bhaskar Vundurthy; K. Sridharan 001 (IEEE Trans. Ind. Informatics, 2020)

A High-Performance VLSI Architecture for a Self-Feedback Convolutional Neural Network. - Yashrajsinh Parmar; K. Sridharan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Bending Angle Sensor Based on Magnetic Coupling Suitable for Soft Robotic Finger. - Debasrita Kar; Boby George; K. Sridharan 001 (SAS, 2022)

Design and Implementation of a Magnetic Coupling Based Segmented Bend Angle Sensor for a Soft Robotic Gripper. - Debasrita Kar; Boby George; K. Sridharan 001 (IEEE Trans. Instrum. Meas., 2024)