Parallel counter design using four-valued threshold logic. - K. Wayne Current; Douglas A. Mow (ICASSP, 1978)

Four-valued threshold logic full adder circuit implementations. - K. Wayne Current; Douglas A. Mow (MVL, 1978)

Applications of multivalued threshold logic in large-scale-intergrated, digital signal processing circuits. - K. Wayne Current; Douglas A. Mow (MVL, 1978)

A high data rate, low power all-digital correlation circuit design. - K. Wayne Current; Douglas A. Mow; S. Youssef-Digaleh (ICASSP, 1979)

Implementing Parallel Counters with Four-Valued Threshold Logic. - K. Wayne Current; Douglas A. Mow (IEEE Trans. Computers, 1979)

High Density Integrated Computing Circuitry with Multiple Valued Logic. - K. Wayne Current (IEEE Trans. Computers, 1980)

Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders. - K. Wayne Current (IEEE Trans. Computers, 1980)

A High Data-Rate Digital Output Correlator Design. - K. Wayne Current (IEEE Trans. Computers, 1980)

Response change in linearized circuits and systems: Computational algorithms and applications. - Stephen B. Haley; K. Wayne Current (Proc. IEEE, 1985)

Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits. - James L. Mangin; K. Wayne Current (IEEE Trans. Computers, 1986)

A unified DCT/IDCT architecture for VLSI implementation. - J. R. Parkhurst; K. Wayne Current; Anil K. Jain 002; J. E. Grishaw (ICASSP, 1988)

A Radon transform computer for multidimensional signal processing. - Stephen G. Azevedo; James M. Brase; Harry E. Martz; Anil K. Jain 002; K. Wayne Current; Paul J. Hurst (ICASSP, 1989)

An architecture for region boundary extraction in raster scan images suitable for VLSI implementation. - James M. Apffel; K. Wayne Current; Jorge L. C. Sanz; Anil K. Jain 002 (Mach. Vis. Appl., 1989)

A VLSI architecture for two-dimensional Radon transform computations. - Paul J. Hurst; K. Wayne Current; Iskender Agi; Eric Shieh (ICASSP, 1990)

A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch. - K. Wayne Current (ISMVL, 1990)

An evaluation of Radon transform computations using DSP chips. - K. Wayne Current; Paul J. Hurst; Eric Shieh; Iskender Agi (Mach. Vis. Appl., 1990)

A new VLSI architecture for real-time control of robot manipulators. - J. Liu; Ziqiang Mao; G. Z. Lu; W. H. Han; Tien C. Hsia; K. Wayne Current; Wei-Shang Chu (ICRA, 1991)

A Bi-Directional Current-Mode CMOS Multiple-Valued Logic Memory Circuit. - K. Wayne Current; M. E. Hurlston (ISMVL, 1991)

A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter Circuit. - K. Wayne Current (ISMVL, 1992)

High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture. - Eric Shieh; K. Wayne Current; Paul J. Hurst; Iskender Agi (IEEE Trans. Circuits Syst. Video Technol., 1992)

Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICs. - K. Wayne Current; James F. Parker; Wes Hardaker (ISCAS, 1993)

Multiple Valued Logic: Current-Mode CMOS Circuits. - K. Wayne Current (ISMVL, 1993)

An image processing IC for backprojection and spatial histogramming in a pipelined array. - Iikender Agi; Paul J. Hurst; K. Wayne Current (IEEE J. Solid State Circuits, 1993)

Quaternary Multiplier Circuit. - Wei-Shang Chu; K. Wayne Current (ISMVL, 1994)

Current-mode CMOS multiple-valued logic circuits. - K. Wayne Current (IEEE J. Solid State Circuits, 1994)

Memory Circuits for Multiple-Valued Logic Voltage Signals. - K. Wayne Current (ISMVL, 1995)

A CMOS continuous-time NTSC-to-color-difference decoder. - James F. Parker; K. Wayne Current; Stephen H. Lewis (IEEE J. Solid State Circuits, 1995)

Low-Energy Logic Circuit Techniques for Multiple-Valued Logic. - K. Wayne Current; Vojin G. Oklobdzija; Dragan Maksimovic (ISMVL, 1996)

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results. - Dragan Maksimovic; Vojin G. Oklobdzija; Borivoje Nikolic; K. Wayne Current (ISLPED, 1997)

CMOS implementation of low-power oscillators based on the modified Fabre-Normand current conveyor. - Jelena Popovic; Borivoje Nikolic; K. Wayne Current; Aleksandra Pavasovic; Dragan Vasiljevic (ICECS, 1998)

Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch. - K. Wayne Current (ISMVL, 2000)

Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts. - Dan Olson; K. Wayne Current (ISMVL, 2000)

Partitioned Branch Condition Resolution Logic. - Aamir A. Farooqui; K. Wayne Current; Vojin G. Oklobdzija (SBCCI, 2000)

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. - Dragan Maksimovic; Vojin G. Oklobdzija; Borivoje Nikolic; K. Wayne Current (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Voltage Comparator Circuits for Multiple-Valued CMOS Logic. - Yongjian Brandon Guo; K. Wayne Current (ISMVL, 2002)

Low-Power Voltage Comparator Circuit for CMOS Quaternary Logic. - Yongjian Brandon Guo; K. Wayne Current (J. Multiple Valued Log. Soft Comput., 2004)

A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor. - K. Wayne Current; Kelvin Yuk; Charles McConaghy; Peter R. C. Gascoyne; Jon A. Schwartz; Jody V. Vykoukal; Craig Andrews (ICMENS, 2005)

A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. - Marko Aleksic; Nikola Nedovic; K. Wayne Current; Vojin G. Oklobdzija (PATMOS, 2005)

A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System. - K. Wayne Current; Kelvin Yuk; Charles McConaghy; Peter R. C. Gascoyne; Jon A. Schwartz; Jody V. Vykoukal; Craig Andrews (IEEE Trans. Biomed. Circuits Syst., 2007)

Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits. - Marko Aleksic; Nikola Nedovic; K. Wayne Current; Vojin G. Oklobdzija (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)