A DC-offset-compensated, CT/DT hybrid filter with process-insensitive cutoff and low in-band group-delay variation for WLAN receivers. - Ka-Fai Un; Pui-In Mak; Rui Paulo da Silva Martins (APCCAS, 2008)

An Open-loop Octave-phase Local-oscillator Generator with High-precision Correlated Phases for VHF/UHF Mobile-TV Tuners. - Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (ISCAS, 2009)

SC biquad filter with hybrid utilization of OpAmp and comparator-based circuit. - Miguel A. Martins; Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (ISCAS, 2010)

Analysis and Design of Open-Loop Multiphase Local-Oscillator Generator for Wireless Applications. - Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A highly-linear ultra-wideband balun-LNA for cognitive radios. - Weng-Fai Cheng; Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (EUROCON, 2011)

A 53-to-75-mW, 59.3-dB HRR, TV-Band White-Space Transmitter Using a Low-Frequency Reference LO in 65-nm CMOS. - Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2013)

A Nonrecursive Digital Calibration Technique for Joint Elimination of Transmitter and Receiver I/Q Imbalances With Minimized Add-On Hardware. - Wei-Han Yu; Chak-Fong Cheang; Pui-In Mak; Weng-Fai Cheng; Ka-Fai Un; U-Wai Lok; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth. - Chak-Fong Cheang; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Time-domain I/Q-LOFT compensator using a simple envelope detector for a sub-GHz IEEE 802.11af WLAN transmitter. - Chak-Fong Cheang; Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (ASP-DAC, 2016)

Overview of Recent Development on Wireless Sensing Circuits and Systems for Healthcare and Biomedical Applications. - Changzhi Li; Ka-Fai Un; Pui-In Mak; Ying Chen; José Maria Muñoz-Ferreras; Zhi Yang 002; Roberto Gómez-García (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

A 0.7-2.5 GHz, 61% EIRP System Efficiency, Four-Element MIMO TX System Exploiting Integrated Power-Relaxed Power Amplifiers and an Analog Spatial De-Interleaver. - Wei-Han Yu; Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios. - Ka-Fai Un; Gengzhen Qi; Jun Yin 001; Shiheng Yang; Shupeng Yu; Chio-In Ieong; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection. - Ka-Fai Un; Feifei Zhang; Pui-In Mak; Rui Paulo Martins; Anding Zhu; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement. - Jixuan Li; Jiabao Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2021)

An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications. - Jixuan Li; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting. - Feifei Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (APCCAS, 2022)

A 108nW 0.8mm2 Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS. - Feifei Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (ISSCC, 2022)

A 108-nW 0.8-mm2 Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS. - Feifei Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

An FPGA-Based Energy-Efficient Reconfigurable Depthwise Separable Convolution Accelerator for Image Recognition. - Lei Xuan; Ka-Fai Un; Chi-Seng Lam; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature Extractor and an RNN Classifier. - Jinhai Lin; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications. - Zhongyu Zhao; Rujian Cao; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 47-nW Voice Activity Detector (VAD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-Volatile CAP-ROM. - Jinhai Lin; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2023)

Invited Paper: A Ping-Pong Analog Delta Generator for Delt-Sigma Computing-In-Memory SRAM Macro for Edge AI Processing. - Ran Zhang; Ka-Fai Un; Zhensheng Li; Mingqiang Guo; Liang Qi 002; Rui Paulo Martins; Sai-Weng Sin (ICTA, 2024)

A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation. - Ran Zhang; Ka-Fai Un; Mingqiang Guo; Liang Qi 002; Dengke Xu; Weibing Zhao; Rui Paulo Martins; Franco Maloberti; Sai-Weng Sin (ISCAS, 2024)

17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM. - Fei Tan; Wei-Han Yu; Jinhai Lin; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization. - Guoqiang Xin; Fei Tan; Junde Li; Junren Chen; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (MWSCAS, 2024)

A 0.05-mm2 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS. - Fei Tan; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing. - Yaozhong Ou; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm2 Analog Compute-in-Memory Macro. - Yuzhao Fu; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001; Minglei Zhang; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 28-nm 18.7 TOPS/mm² 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh. - Yi Zhan; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization. - Yuzhao Fu; Jixuan Li; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications. - Rujian Cao; Zhongyu Zhao; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 512-nW 0.003-mm² Forward-Forward Closed Box Trainer for an Analog Voice Activity Detector in 28-nm CMOS. - Junde Li; Guoqiang Xin; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Keyword-Spotting(KWS) Chip Featuring a Bio-Inspired Neuron Model in 65-nm CMOS. - Yantong Liu; Fei Tan; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (CNIOT, 2025)

A 94.8nW Battery-Free Intelligent Silicon Platform Enabling Distributed, Adaptive, and Event-Driven Multimodal Sensing at the Edge. - Haochen Zhang; Wei-Han Yu; Zhongyu Zhao; Zhizhan Yang; Ka-Fai Un; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2025)

A 90.7-nW Vibration-Based Condition Monitoring Chip Featuring a Digital Compute-in-Memory- Based DNN Accelerator Using an Ultra-Low-Power 13T-SRAM Cell. - Haochen Zhang; Wei-Han Yu; Zhizhan Yang; Ka-Fai Un; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM. - Fei Tan; Wei-Han Yu; Jinhai Lin; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow. - Yi Zhan; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 28-nm MFCC-Free Keyword Switchable Keyword Spotting (KWS) System With Transferred Training Algorithm. - Fei Tan; Yujia Wang; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation. - Ran Zhang; Xueru Cen; Ka-Fai Un; Mingqiang Guo; Liang Qi 002; Rui Paulo Martins; Sai-Weng Sin (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

An 800-MHz 8.17-TOPS/W 0.63-TOPS/mm2 Memory-Utilization-Aware CNN Accelerator Featuring a Memory Stationary Dataflow. - Jixuan Li; Ke Li; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization. - Jixuan Li; Ke Li; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)