Efficient Hardware Accelerators for the Computation of Tchebichef Moments. - Kah-Hyong Chang; Paramesran Raveendran; Barmak Honarvar Shakibaei Asli; Chern-Loon Lim (IEEE Trans. Circuits Syst. Video Technol., 2012)

An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing. - Xin Liu 015; Jun Zhou 017; Chao Wang 016; Kah-Hyong Chang; Jianwen Luo; Jingjing Lan; Lei Liao; Yat-Hei Lam; Yongkui Yang; Bo Wang 020; Xin Zhang 025; Wang Ling Goh; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Configurable Architecture for Fast Moments Computation. - Kah-Hyong Chang; Paramesran Raveendran (J. Signal Process. Syst., 2015)

A rail-to-rail noise-shaping non-binary SAR ADC. - S. Saisundar; N. Yoshio; Kah-Hyong Chang (ISIC, 2016)