A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process. - Kuo-Hsing Cheng; Kai-Fei Chang; Yu-Lung Lo; Ching-Wen Lai; Yuh-Kuang Tseng (ISCAS, 2006)

A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation. - Kuo-Hsing Cheng; Chia-Wei Su; Kai-Fei Chang (IEEE J. Solid State Circuits, 2008)