Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264. - Kai Huang 002; Sang-Il Han; Katalin Popovici; Lisane B. de Brisolara; Xavier Guerin; Lei Li; Xiaolang Yan; Soo-Ik Chae; Luigi Carro; Ahmed Amine Jerraya (DAC, 2007)

Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation. - Sang-Il Han; Soo-Ik Chae; Lisane B. de Brisolara; Luigi Carro; Katalin Popovici; Xavier Guerin; Ahmed Amine Jerraya; Kai Huang 002; Lei Li; Xiaolang Yan (Integr., 2009)

A high efficient memory architecture for H.264/AVC motion compensation. - Chunshu Li; Kai Huang 002; Xiaolang Yan; Jiong Feng; De Ma; Haitong Ge (ASAP, 2010)

Communication Pipelining for Code Generation from Simulink Models. - Rongjie Yan; Kai Huang 002; Min Yu 006; Xiaomeng Zhang (TrustCom/ISPA/IUCC, 2013)

High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding (CABAC) decoding. - Kai Huang 002; De Ma; Rongjie Yan; Haitong Ge; Xiaolang Yan (J. Zhejiang Univ. Sci. C, 2013)

Performance Estimation Techniques With MPSoC Transaction-Accurate Models. - De Ma; Rongjie Yan; Kai Huang 002; Min Yu 006; Siwen Xiu; Haitong Ge; Xiaolang Yan; Ahmed Amine Jerraya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Annotation and analysis combined cache modeling for native simulation. - Rongjie Yan; De Ma; Kai Huang 002; Xiaoxu Zhang; Siwen Xiu (ASP-DAC, 2014)

Automatic cache partitioning and time-triggered scheduling for real-time MPSoCs. - Gang Chen 023; Biao Hu 001; Kai Huang 001; Alois C. Knoll; Kai Huang 002; Di Liu 002; Todor P. Stefanov (ReConFig, 2014)

ILP Based Multithreaded Code Generation for Simulink Model. - Kai Huang 002; Min Yu 006; Xiaomeng Zhang; Dandan Zheng 001; Siwen Xiu; Rongjie Yan; Kai Huang 001; Zhili Liu; Xiaolang Yan (IEICE Trans. Inf. Syst., 2014)

Communication-oriented performance optimisation during code generation from Simulink models. - Rongjie Yan; Min Yu 006; Kai Huang 002; Xiaomeng Zhang (Int. J. Embed. Syst., 2014)

Hybrid Model: An Efficient Symmetric Multiprocessor Reference Model. - Shupeng Wang; Kai Huang 002; Tianyi Xie; Xiaolang Yan (J. Electr. Comput. Eng., 2015)

Profiling and annotation combined method for multimedia application specific MPSoC performance estimation. - Kai Huang 002; Xiaoxu Zhang; Siwen Xiu; Dan-dan Zheng 001; Min Yu 006; De Ma; Kai Huang 001; Gang Chen 023; Xiaolang Yan (Frontiers Inf. Technol. Electron. Eng., 2015)

Communication Optimizations for Multithreaded Code Generation from Simulink Models. - Kai Huang 002; Min Yu 006; Rongjie Yan; Xiaomeng Zhang; Xiaolang Yan; Lisane B. de Brisolara; Ahmed Amine Jerraya; Jiong Feng (ACM Trans. Embed. Comput. Syst., 2015)

Functional Testbench Qualification by Mutation Analysis. - Kai Huang 002; Peng Zhu; Rongjie Yan; Xiaolang Yan (VLSI Design, 2015)

SoC and FPGA oriented high-quality stereo vision system. - Yanzhe Li; Kai Huang 002; Luc Claesen (FPL, 2016)

SoC oriented real-time high-quality stereo vision system. - Yanzhe Li; Kai Huang 002; Luc Claesen (VLSI-SoC, 2016)

A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture Design in FPGA. - Yanzhe Li; Kai Huang 002; Luc Claesen (VLSI-SoC (Selected Papers), 2016)

Reconfigurable cache for real-time MPSoCs: Scheduling and implementation. - Gang Chen 023; Biao Hu 001; Kai Huang 001; Alois C. Knoll; Kai Huang 002; Di Liu 002; Todor P. Stefanov; Feng Li (Microprocess. Microsystems, 2016)

Improving the efficiency of functional verification based on test prioritization. - Shupeng Wang; Kai Huang 002 (Microprocess. Microsystems, 2016)

Memory Access Scheduling Based on Dynamic Multilevel Priority in Shared DRAM Systems. - Dongliang Xiong; Kai Huang 002; Xiaowen Jiang 001; Xiaolang Yan (ACM Trans. Archit. Code Optim., 2016)

High-quality view interpolation based on depth maps and its hardware implementation. - Yanzhe Li; Kai Huang 002; Luc Claesen (FPL, 2017)

User Perceived Value-Aware Cloud Pricing for Profit Maximization of Multiserver Systems. - Peijin Cong; Liying Li 002; Gaoyuan Shao; Junlong Zhou; Mingsong Chen 001; Kai Huang 002; Tongquan Wei (ICPADS, 2017)

A Hybrid Multi-objective Evolutionary Algorithm for Energy-Aware Allocation and Scheduling Optimization of MPSoCs. - Rongjie Yan; Yupeng Zhou; Yige Yan; Minghao Yin; Min Yu 006; Feifei Ma; Kai Huang 002 (ICTAI, 2017)

Providing Predictable Performance via a Slowdown Estimation Model. - Dongliang Xiong; Kai Huang 002; Xiaowen Jiang 001; Xiaolang Yan (ACM Trans. Archit. Code Optim., 2017)

Detection of movement-related cortical potentials associated with emergency and non-emergency tasks. - Shengtao Li; Yuzhang Zhu; Gan Huang; Liangjun Zhang; Zhiguo Zhang 001; Kai Huang 002 (DSP, 2018)

The Recognition of Driving Action Based on EEG Signals Using Wavelet-CSP Algorithm. - Jinxin Lin; Shunyu Liu 001; Gan Huang; Zhiguo Zhang 001; Kai Huang 002 (DSP, 2018)

Energy-Efficient Fault-Tolerant Mapping and Scheduling on Heterogeneous Multiprocessor Real-Time Systems. - Kai Huang 002; Xiaowen Jiang 001; Xiaomeng Zhang; Rongjie Yan; Ke Wang 034; Dongliang Xiong; Xiaolang Yan (IEEE Access, 2018)

BFCO: A BPSO-Based Fine-Grained Communication Optimization Method for MPSoC. - Xiaomeng Zhang; Kai Huang 002; Min Yu 006; Xiaowen Jiang 001; Xiaolang Yan (IEEE Access, 2018)

Curve fitting based shared cache partitioning scheme for energy saving. - Kai Huang 002; Ke Wang 034; Xiaoxu Zhang; Xiaolang Yan (IEICE Electron. Express, 2018)

NoUCSR: Efficient Super-Resolution Network without Upsampling Convolution. - Dongliang Xiong; Kai Huang 002; Siang Chen; Bowen Li 017; Haitian Jiang; Wenyuan Xu 001 (ICCV Workshops, 2019)

Fine-Grained Communication-Aware Task Scheduling Approach for Acyclic and Cyclic Applications on MPSoCs. - Kai Huang 002; Xiaowen Jiang 001; Haitian Jiang; Xiaomeng Zhang; Min Yu 006; Rongjie Yan; Xiaolang Yan (IEEE Access, 2019)

Holistic hardware Trojan design of trigger and payload at gate level with rare switching signals eliminated. - Kai Huang 002; Yun He; Xiaowen Jiang 001 (IEICE Electron. Express, 2019)

A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC Considering Load Balance and Communication Optimization. - Kai Huang 002; Xiaomeng Zhang; Dandan Zheng 001; Min Yu 006; Xiaowen Jiang 001; Xiaolang Yan; Lisane B. de Brisolara; Ahmed Amine Jerraya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A Real-Time High-Quality Complete System for Depth Image-Based Rendering on FPGA. - Yanzhe Li; Luc Claesen; Kai Huang 002; Menglian Zhao (IEEE Trans. Circuits Syst. Video Technol., 2019)

DFQF: Data Free Quantization-aware Fine-tuning. - Bowen Li 017; Kai Huang 002; Siang Chen; Dongliang Xiong; Haitian Jiang; Luc Claesen (ACML, 2020)

Adaptive Hybrid Composition Based Super-Resolution Network via Fine-Grained Channel Pruning. - Siang Chen; Kai Huang 002; Bowen Li 017; Dongliang Xiong; Haitian Jiang; Luc Claesen (ECCV Workshops (3), 2020)

IdleSR: Efficient Super-Resolution Network with Multi-scale IdleBlocks. - Dongliang Xiong; Kai Huang 002; Haitian Jiang; Bowen Li 017; Siang Chen; Xiaowen Jiang 001 (ECCV Workshops (3), 2020)

Fine-Grained Channel Pruning for Deep Residual Neural Networks. - Siang Chen; Kai Huang 002; Dongliang Xiong; Bowen Li 017; Luc Claesen (ICANN (2), 2020)

Trigger Identification Using Difference-Amplified Controllability and Dynamic Transition Probability for Hardware Trojan Detection. - Kai Huang 002; Yun He (IEEE Trans. Inf. Forensics Secur., 2020)

DPOQ: Dynamic Precision Onion Quantization. - Bowen Li 017; Kai Huang 002; Siang Chen; Dongliang Xiong; Luc Claesen (ACML, 2021)

Expected Energy Optimization for Real-Time Multiprocessor SoCs Running Periodic Tasks with Uncertain Execution Time. - Kai Huang 002; Ke Wang 034; Dandan Zheng 001; Xiaowen Jiang 001; Xiaomeng Zhang; Rongjie Yan; Xiaolang Yan (IEEE Trans. Sustain. Comput., 2021)

Halftoning with Multi-Agent Deep Reinforcement Learning. - Haitian Jiang; Dongliang Xiong; Xiaowen Jiang 001; Aiguo Yin; Li Ding; Kai Huang 002 (ICIP, 2022)

Sample-wise dynamic precision quantization for neural network acceleration. - Bowen Li 017; Dongliang Xiong; Kai Huang 002; Xiaowen Jiang 001; Hao Yao; Junjian Chen; Luc Claesen (IEICE Electron. Express, 2022)

Structured precision skipping: Accelerating convolutional neural networks with budget-aware dynamic precision selection. - Kai Huang 002; Siang Chen; Bowen Li 017; Luc Claesen; Hao Yao; Junjian Chen; Xiaowen Jiang 001; Zhili Liu; Dongliang Xiong (J. Syst. Archit., 2022)

Flexible and Dynamic Scheduling of Mixed-Criticality Systems. - Xiaowen Jiang 001; Tianyi Sha; Dehong Liu; Junjian Chen; Chen Chen; Kai Huang 002 (Sensors, 2022)

Acceleration-Aware Fine-Grained Channel Pruning for Deep Neural Networks via Residual Gating. - Kai Huang 002; Siang Chen; Bowen Li 017; Luc Claesen; Hao Yao; Junjian Chen; Xiaowen Jiang 001; Zhili Liu; Dongliang Xiong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A 1.8V 16μA 136.5dB DR PPG/NIRS Recording IC using Noise Shaping Triple Slope Light to Digital Converter. - Mengyu Li; Shuang Song 003; Dehong Wang; Feijun Zheng; Tian Yang; Yalong Wan; Kai Huang 002; Zhichao Tan; Menglian Zhao (CICC, 2023)

SILL: Preventing structural attack for logic locking. - Jihu Liang; Ke Wang 034; Wei Xi; Changbao Xu; Junjian Chen; Kai Huang 002 (IEICE Electron. Express, 2023)

Fast halftoning policy network with error feedback. - Haitian Jiang; Dongliang Xiong; Aiguo Yin; Li Ding; Kai Huang 002 (J. Electronic Imaging, 2023)

Structured Term Pruning for Computational Efficient Neural Networks Inference. - Kai Huang 002; Bowen Li 017; Siang Chen; Luc Claesen; Wei Xi; Junjian Chen; Xiaowen Jiang 001; Zhili Liu; Dongliang Xiong; Xiaolang Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Efficient Halftoning via Deep Reinforcement Learning. - Haitian Jiang; Dongliang Xiong; Xiaowen Jiang 001; Li Ding; Liang Chen; Kai Huang 002 (IEEE Trans. Image Process., 2023)

Structured Dynamic Precision for Deep Neural Networks Quantization. - Kai Huang 002; Bowen Li 017; Dongliang Xiong; Haitian Jiang; Xiaowen Jiang 001; Xiaolang Yan; Luc Claesen; Dehong Liu; Junjian Chen; Zhili Liu (ACM Trans. Design Autom. Electr. Syst., 2023)

BISHENG: A 49.38PPM Flexible Multi-Function Printer SoC in 28nm CMOS. - Dongliang Xiong; Xiaoxu Zhang; Siwen Xiu; Zhili Liu; Dandan Zheng 001; Li Ding; Aiguo Yin; Peiyong Zhang; Kai Huang 002 (ICTA, 2024)

FCLock: harnessing functional non-combinational cycles in logic locking. - Xiang Chen; Dandan Zheng 001; Kai Huang 002 (IEICE Electron. Express, 2024)

Structural analysis attack on asynchronous obfuscated circuits. - Zihe Wang; Dongliang Xiong; Kai Huang 002 (IEICE Electron. Express, 2024)

A novel crosstalk based dynamic camouflage technique for preventing reverse engineering. - Guotao Zhan; Dandan Zheng 001; Kai Huang 002 (IEICE Electron. Express, 2024)

Low-Power On-Chip Energy Harvesting: From Interface Circuits Perspective. - Shuang Song 003; Dehong Wang; Mengyu Li; Siyao Cao; Feijun Zheng; Kai Huang 002; Zhichao Tan; Sijun Du; Menglian Zhao (IEEE Open J. Circuits Syst., 2024)

A Response-Feedback-Based Strong PUF with Improved Strict Avalanche Criterion and Reliability. - Baokui Zhu; Xiaowen Jiang 001; Kai Huang 002; Miao Yu 002 (Sensors, 2024)

A 20.3μW 1.9GΩ Input Impedance Capacitively-Coupled Chopper-Stabilized Amplifier for Bio-Potential Readout. - Yizhao Zhou; Shuang Song 003; Yu Zheng; Tian Yang; Mengyu Li; Yipeng Cao; Feijun Zheng; Kai Huang 002; Zhichao Tan; Menglian Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 30-μW 94.7-dB SNDR Noise-Shaping Current-Mode Direct-to-Digital Converter Using Triple-Slope Quantizer for PPG/NIRS Readout. - Mengyu Li; Shuang Song 003; Dehong Wang; Tian Yang; Yu Zheng; Qiuyang Lin; Feijun Zheng; Kai Huang 002; Zhichao Tan; Menglian Zhao (IEEE J. Solid State Circuits, 2024)

Blade-DA: Click-Based Asynchronous Resilient Circuit With Dynamic Delay Adjustment. - Chenghong Zhang; Dongliang Xiong; Xiaoxu Zhang; Kai Huang 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Adaptive Input Voltage Current-Balanced Analog Frontend System for Multiple Cell Li-ion Battery Electrochemical Impedance Monitoring. - Yutong Zhang; Dehong Wang; Jiankao Pan; Quan Chen; Chen Chen; Yulu Zhang; Kai Huang 002; Menglian Zhao; Shuang Song 003 (ISCAS, 2025)

A low-overhead resilient circuit with partial two-phase latch. - Chenghong Zhang; Dongliang Xiong; Kai Huang 002 (IEICE Electron. Express, 2025)

ATEP: An Asynchronous Timing Error Prediction Circuit With Adaptive Voltage and Frequency Scaling. - Chenghong Zhang; Dongliang Xiong; Xiaoxu Zhang; Zhengyu Wang; Huibo Gao; Kai Huang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2025)