A Temporal Assertion Extension to Verilog. - Kai-Hui Chang; Wei-Ting Tu; Yi-Jong Yeh; Sy-Yen Kuo (ATVA, 2004)

Automatic Partitioner for Behavior Level Distributed Logic Simulation. - Kai-Hui Chang; Jeh-Yen Kang; Han-Wei Wang; Wei-Ting Tu; Yi-Jong Yeh; Sy-Yen Kuo (FORTE, 2005)

Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. - Kai-Hui Chang; Igor L. Markov; Valeria Bertacco (ICCAD, 2005)

Safe Delay Optimization for Physical Synthesis. - Kai-Hui Chang; Igor L. Markov; Valeria Bertacco (ASP-DAC, 2007)

Node Mergers in the Presence of Don't Cares. - Stephen Plaza; Kai-Hui Chang; Igor L. Markov; Valeria Bertacco (ASP-DAC, 2007)

Automatic error diagnosis and correction for RTL designs. - Kai-Hui Chang; Ilya Wagner; Valeria Bertacco; Igor L. Markov (HLDVT, 2007)

Automating post-silicon debugging and repair. - Kai-Hui Chang; Igor L. Markov; Valeria Bertacco (ICCAD, 2007)

InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. - Kai-Hui Chang; David A. Papa; Igor L. Markov; Valeria Bertacco (ISQED, 2007)

Simulation-Based Bug Trace Minimization With BMC-Based Refinement. - Kai-Hui Chang; Valeria Bertacco; Igor L. Markov (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Postplacement rewiring by exhaustive search for functional symmetries. - Kai-Hui Chang; Igor L. Markov; Valeria Bertacco (ACM Trans. Design Autom. Electr. Syst., 2007)

Functional design error diagnosis, correction and layout repair of digital circuits. - Kai-Hui Chang (2007)

Reap what you sow: spare cells for post-silicon metal fix. - Kai-Hui Chang; Igor L. Markov; Valeria Bertacco (ISPD, 2008)

Automating Postsilicon Debugging and Repair. - Kai-Hui Chang; Igor L. Markov; Valeria Bertacco (Computer, 2008)

SafeResynth: A new technique for physical synthesis. - Kai-Hui Chang; Igor L. Markov; Valeria Bertacco (Integr., 2008)

Fixing Design Errors With Counterexamples and Resynthesis. - Kai-Hui Chang; Igor L. Markov; Valeria Bertacco (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Handling don't-care conditions in high-level synthesis and application for reducing initialized registers. - Hong-Zu Chou; Kai-Hui Chang; Sy-Yen Kuo (DAC, 2009)

Customizing IP cores for system-on-chip designs using extensive external don't-cares. - Kai-Hui Chang; Valeria Bertacco; Igor L. Markov (DATE, 2009)

Enhancing bug hunting using high-level symbolic simulation. - Hong-Zu Chou; I-Hui Lin; Ching-Sung Yang; Kai-Hui Chang; Sy-Yen Kuo (ACM Great Lakes Symposium on VLSI, 2009)

Incremental Verification with Error Detection, Diagnosis, and Visualization. - Kai-Hui Chang; David A. Papa; Igor L. Markov; Valeria Bertacco (IEEE Des. Test Comput., 2009)

Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair - Kai-Hui Chang; Igor L. Markov; Valeria Bertacco (Springer, 2009)

Optimizing blocks in an SoC using symbolic code-statement reachability analysis. - Hong-Zu Chou; Kai-Hui Chang; Sy-Yen Kuo (ASP-DAC, 2010)

Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study. - Hong-Zu Chou; Haiqian Yu; Kai-Hui Chang; Dylan Dobbyn; Sy-Yen Kuo (DATE, 2010)

Accurately Handle Don't-Care Conditions in High-Level Designs and Application for Reducing Initialized Registers. - Hong-Zu Chou; Kai-Hui Chang; Sy-Yen Kuo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Logic synthesis and circuit customization using extensive external don't-cares. - Kai-Hui Chang; Valeria Bertacco; Igor L. Markov; Alan Mishchenko (ACM Trans. Design Autom. Electr. Syst., 2010)

Facilitating unreachable code diagnosis and debugging. - Hong-Zu Chou; Kai-Hui Chang; Sy-Yen Kuo (ASP-DAC, 2011)

Formal reset recovery slack calculation at the register transfer level. - Chih-Neng Chung; Chia-Wei Chang; Kai-Hui Chang; Sy-Yen Kuo (DATE, 2011)

Applying verification intention for design customization via property mining under constrained testbenches. - Chih-Neng Chung; Chia-Wei Chang; Kai-Hui Chang; Sy-Yen Kuo (ICCD, 2011)

Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization. - Chia-Wei Chang; Hong-Zu Chou; Kai-Hui Chang; Jie-Hong Roland Jiang; Chien-Nan Jimmy Liu; Chiu-Han Hsiao; Sy-Yen Kuo (ISQED, 2011)

Improving gate-level simulation accuracy when unknowns exist. - Kai-Hui Chang; Chris Browy (DAC, 2012)

RTL analysis and modifications for improving at-speed test. - Kai-Hui Chang; Hong-Zu Chou; Igor L. Markov (DATE, 2012)

Improving design verifiability by early RTL coverability analysis. - Kai-Hui Chang; Chia-Wei Chang; Jie-Hong Roland Jiang; Chien-Nan Jimmy Liu (MEMOCODE, 2012)

Reducing test point overhead with don't-cares. - Kai-Hui Chang; Chia-Wei Chang; Jie-Hong Roland Jiang; Chien-Nan Jimmy Liu (MWSCAS, 2012)

Parallel Logic Simulation: Myth or Reality? - Kai-Hui Chang; Chris Browy (Computer, 2012)

Automated methods for eliminating X bugs. - Kai-Hui Chang; Yen-Ting Liu; Chris Browy (ISQED, 2014)

Scalable sequence-constrained retention register minimization in power gating design. - Ting-Wei Chiang; Kai-Hui Chang; Yen-Ting Liu; Jie-Hong R. Jiang (DAC, 2015)

Handling Nondeterminism in Logic Simulation so That Your Waveform Can Be Trusted Again. - Kai-Hui Chang; Hong-Zu Chou; Haiqian Yu; Dylan Dobbyn; Sy-Yen Kuo (IEEE Des. Test, 2016)

Path controllability analysis for high quality designs. - Li-Jie Chen; Hong-Zu Chou; Kai-Hui Chang; Sy-Yen Kuo; Chi-Lai Huang (ASP-DAC, 2019)