Multiple-Precision Floating-Point Dot Product Unit for Efficient Convolution Computation. - Kai Li 024; Wei Mao 002; Xinang Xie; Quan Cheng; Huan Xie; Zhenjiang Dong; Hao Yu 001 (AICAS, 2021)

A Reconfigurable Multiple-Precision Floating-Point Dot Product Unit for High-Performance Computing. - Wei Mao 002; Kai Li 024; Xinang Xie; Shirui Zhao; He Li 008; Hao Yu 001 (DATE, 2021)

A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing. - Kai Li 024; Junzhuo Zhou; Boyu Li; Shuxing Yang; Sixiao Huang; Shaobo Luo; Wei Mao 002; Hao Yu 001 (AICAS, 2022)

An Energy-Efficient Bit-Split-and-Combination Systolic Accelerator for NAS-Based Multi-Precision Convolution Neural Networks. - Liuyao Dai; Quan Cheng; Yuhang Wang; Gengbin Huang; Junzhuo Zhou; Kai Li 024; Wei Mao 002; Hao Yu 001 (ASP-DAC, 2022)

A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge. - Kai Li 024; Junzhuo Zhou; Yuhang Wang; Junyi Luo; Zhengke Yang; Shuxin Yang; Wei Mao 002; Mingqiang Huang; Hao Yu 001 (DATE, 2022)

A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA. - Mingqiang Huang; Yucen Liu; Quan Cheng; Shuxin Yang; Kai Li 024; Junyi Luo; Zhengke Yang; Qiufeng Li; Hao Yu 001; Changhai Man (FPGA, 2022)

A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks. - Mingqiang Huang; Yucen Liu; Changhai Man; Kai Li 024; Quan Cheng; Wei Mao 002; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing. - Kai Li 024; Wei Mao 002; Junzhuo Zhou; Boyu Li; Zhengke Yang; Shuxing Yang; Laimin Du; Sixiao Huang; Hao Yu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks. - Wei Mao 002; Liuyao Dai; Kai Li 024; Quan Cheng; Yuhang Wang; Laimin Du; Shaobo Luo; Mingqiang Huang; Hao Yu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing. - Wei Mao 002; Kai Li 024; Quan Cheng; Liuyao Dai; Boyu Li; Xinang Xie; He Li 008; Longyang Lin; Hao Yu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

RISC-V based Fully-Parallel SRAM Computing-in-Memory Accelerator with High Hardware Utilization and Data Reuse Rate. - Haoxiang Zhou; Haiqiao Hong; Dingbang Liu; Hang Liu; Yu Xia; Kai Li 024; Jun Liu; Shaobo Luo; Wei Mao 002; Hao Yu 001 (AICAS, 2023)

Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme. - Mingqiang Huang; Yucen Liu; Sixiao Huang; Kai Li 024; Qiuping Wu; Hao Yu 001 (FPGA, 2023)

A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS. - Kai Li 024; Hantao Huang; Mingqiang Huang; Chenchen Ding; Longyang Lin; Liebing Ni; Hao Yu 001 (CICC, 2024)

LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA. - Shuxin Yang; Chenchen Ding; Mingqiang Huang; Kai Li 024; Chenghao Li 010; Zikun Wei; Sixiao Huang; Jingyao Dong; Liuyang Zhang; Hao Yu 001 (FCCM, 2024)

EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models. - Mingqiang Huang; Ao Shen; Kai Li 024; Haoxiang Peng; Boyu Li; Hao Yu 001 (CoRR, 2024)

A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier. - Laimin Du; Leibin Ni; Xiong Liu; Guanqi Peng; Kai Li 024; Wei Mao 002; Hao Yu 001 (IEEE Open J. Circuits Syst., 2024)

A Reconfigurable Processing Element for Multiple-Precision Floating/Fixed-Point HPC. - Boyu Li; Kai Li 024; Jiajun Zhou; Yuan Ren; Wei Mao 002; Hao Yu 001; Ngai Wong 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models. - Mingqiang Huang; Ao Shen; Kai Li 024; Haoxiang Peng; Boyu Li; Yupeng Su; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 28-nm 135.19 TOPS/W Bootstrapped-SRAM Compute-in-Memory Accelerator With Layer-Wise Precision and Sparsity. - Wei Mao 002; Dingbang Liu; Haoxiang Zhou; Fuyi Li; Kai Li 024; Qiuping Wu; Jiaqi Yang; Quan Cheng; Liuyang Zhang; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)