LB-packing-based floorplan design on DBL representation. - Jin-Tai Yan; Kai-Ping Lin; Yue-Fong Luo (ICECS, 2005)

Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation. - Jin-Tai Yan; Kai-Ping Lin; Yen-Hsiang Chen (ISCAS (3), 2005)

Floorplan-aware decoupling capacitance budgeting on equivalent circuit model. - Jin-Tai Yan; Kai-Ping Lin; Yue-Fong Luo (ISCAS, 2006)

eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference. - Chao-Tsung Huang; Yu-Chun Ding; Huan-Ching Wang; Chi-Wen Weng; Kai-Ping Lin; Li-Wei Wang 013; Li-De Chen (MICRO, 2019)

A HD 31fps 7×7-View Light-Field Factorization Processor for Dual-Layer 3D Factored Display. - Li-Qun Weng; Li-De Chen; Hao-Chien Cheng; An-You Zheng; Kai-Ping Lin; Chao-Tsung Huang (ISSCC, 2022)

VISTA: A 704mW 4K-UHD CNN Processor for Video and Image Spatial/Temporal Interpolation Acceleration. - Kai-Ping Lin; Jia-Han Liu; Jyun-Yi Wu; Hong-Chuan Liao; Chao-Tsung Huang (ISSCC, 2023)

VLSI Design of Light-Field Factorization for Dual-Layer Factored Display. - Li-De Chen; Li-Qun Weng; Hao-Chien Cheng; An-Yu Cheng; Kai-Ping Lin; Chao-Tsung Huang (IEEE Trans. Very Large Scale Integr. Syst., 2024)

2.9 STEP: An 8K-60fps Space-Time Resolution-Enhancement Neural-Network Processor for Next-Generation Display and Streaming. - Kai-Ping Lin; Tong Wu; Chang-Pao Lin; Po-Wei Chen; Zhi-Jun Zhang; Win-San Khwa; Meng-Fan Chang; Chao-Tsung Huang (ISSCC, 2025)