On a Binary Relation Inference Network. - Kai-Pui Lam; Crystal J. Su (IPPS, 1991)

Digital Circuit Implementation of a Continuous-time Inference Network for the Transitive Closure Problem. - Crystal J. Su; Kai-Pui Lam (ISCAS, 1993)

A binary relation inference network Part 2. State-space techniques. - Kai-Pui Lam (Int. J. Syst. Sci., 1996)

A continuous-time inference network and its hybrid implementations. - Kai-Pui Lam (Int. J. Syst. Sci., 1996)

A binary relation inference network Part 1. General concepts. - Kai-Pui Lam; Crystal J. Su (Int. J. Syst. Sci., 1996)

On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach. - Kai-Pui Lam; Sui-Tung Mak (FPL, 2002)

Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing. - Sui-Tung Mak; Kai-Pui Lam (FPT, 2002)

Extracting Causation Knowledge from Natural Language Texts. - Ki Chan; Boon Toh Low; Wai Lam; Kai-Pui Lam (PAKDD, 2002)

High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign. - Terrence S. T. Mak; Kai-Pui Lam (CSB, 2003)

An FPGA-based eigenfilter using fast Hebbian learning. - Kai-Pui Lam; Sui-Tung Mak (ICASSP (2), 2003)

Field programmable gate arrays and analog implementation of BRIN for optimization problems. - H. S. Ng; Sui-Tung Mak; Kai-Pui Lam (ISCAS (5), 2003)

Analog and digital FPGA implementation of BRIN for optimization problems. - H. S. Ng; Kai-Pui Lam (IEEE Trans. Neural Networks, 2003)

Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA. - Terrence S. T. Mak; Kai-Pui Lam (CSB, 2004)

FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation. - Terrence S. T. Mak; Kai-Pui Lam (FPL, 2004)

On Computing Maximum Likelihood Phylogeny Using FPGA p. - Terrence S. T. Mak; Kai-Pui Lam (FPL, 2004)

An ICA design of intraday stock prediction models with automatic variable selection. - P. Y. Mok 001; Kai-Pui Lam; H. S. Ng (IJCNN, 2004)

How Does Sample Size Affect GARCH Models? - H. S. Ng; Kai-Pui Lam (JCIS, 2006)

A Current-Mode Analog Circuit for Reinforcement Learning Problems. - Terrence S. T. Mak; Kai-Pui Lam; H. S. Ng; Guy Rachmuth; Chi-Sang Poon (ISCAS, 2007)

A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk; Kai-Pui Lam (NOCS, 2007)

A DP-network for optimal dynamic routing in network-on-chip. - Terrence S. T. Mak; Peter Y. K. Cheung; Wayne Luk; Kai-Pui Lam (CODES+ISSS, 2009)

Intra-daily information of range-based volatility for MEM-GARCH. - Kai-Pui Lam; H. S. Ng (Math. Comput. Simul., 2009)

A CMOS Current-Mode Dynamic Programming Circuit. - Terrence S. T. Mak; Kai-Pui Lam; H. S. Ng; Guy Rachmuth; Chi-Sang Poon (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

On-chip dynamic programming networks using 3D-TSV integration. - Ra'ed Al-Dujaily; Terrence S. T. Mak; Kuan Zhou; Kai-Pui Lam; Yicong Meng; Alexandre Yakovlev; Chi-Sang Poon (ICSAMOS, 2011)

Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC. - Kai-Pui Lam; Terrence S. T. Mak; Chi-Sang Poon (VLSI-SoC, 2011)

Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network. - Kai-Pui Lam; Terrence S. T. Mak; Chi-Sang Poon (VLSI-SoC, 2011)

Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. - Terrence S. T. Mak; Peter Y. K. Cheung; Kai-Pui Lam; Wayne Luk (IEEE Trans. Ind. Electron., 2011)

Dynamic On-Chip Thermal Optimization for Three-Dimensional Networks-On-Chip. - Ra'ed Al-Dujaily; Terrence S. T. Mak; Kai-Pui Lam; Fei Xia 001; Alex Yakovlev; Chi-Sang Poon (Comput. J., 2013)