Kai Wang

Affiliations:
  • University of California, Santa Barbara, Department of Electrical and Computer Engineering, CA, USA


According to our database1, Kai Wang authored at least 10 papers between 2001 and 2005.

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Bibliography

2005
General skew constrained clock network sizing based on sequential linear programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

On-chip power-supply network optimization using multigrid-based technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Clock skew bounds estimation under power supply and process variations.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
Fast postplacement optimization using functional symmetries.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Clock network sizing via sequential linear programming with time-domain analysis.
Proceedings of the 2004 International Symposium on Physical Design, 2004

Potential Slack Budgeting with Clock Skew Optimization.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Buffer sizing for clock power minimization subject to general skew constraints.
Proceedings of the 41th Design Automation Conference, 2004

2003
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique.
Proceedings of the 2003 Design, 2003

2002
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components.
Proceedings of the 2002 Design, 2002

2001
Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques.
Proceedings of the 38th Design Automation Conference, 2001


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