Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques. - Chih-Wei Jim Chang; Kai Wang 011; Malgorzata Marek-Sadowska (DAC, 2001)

Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. - Arindam Mukherjee 001; Kai Wang 011; Lauren Hui Chen; Malgorzata Marek-Sadowska (DATE, 2002)

Power/Ground Mesh Area Optimization Using Multigrid-Based Technique. - Kai Wang 011; Malgorzata Marek-Sadowska (DATE, 2003)

Buffer sizing for clock power minimization subject to general skew constraints. - Kai Wang 011; Malgorzata Marek-Sadowska (DAC, 2004)

Potential Slack Budgeting with Clock Skew Optimization. - Kai Wang 011; Malgorzata Marek-Sadowska (ICCD, 2004)

Clock network sizing via sequential linear programming with time-domain analysis. - Kai Wang 011; Malgorzata Marek-Sadowska (ISPD, 2004)

Fast postplacement optimization using functional symmetries. - Chih-Wei Jim Chang; Ming-Fu Hsiao; Bo Hu 006; Kai Wang 011; Malgorzata Marek-Sadowska; Chung-Kuan Cheng; Sao-Jie Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Clock skew bounds estimation under power supply and process variations. - Hailin Jiang; Kai Wang 011; Malgorzata Marek-Sadowska (ACM Great Lakes Symposium on VLSI, 2005)

On-chip power-supply network optimization using multigrid-based technique. - Kai Wang 011; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

General skew constrained clock network sizing based on sequential linear programming. - Kai Wang 011; Yajun Ran; Hailin Jiang; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)