32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation. - Tzung-Je Lee; Kai-Wei Ruan; Chua-Chin Wang (ICICDT, 2014)

2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation. - Chua-Chin Wang; Zong-You Hou; Kai-Wei Ruan (IEEE Trans. Circuits Syst. II Express Briefs, 2017)