A precise bandgap reference with intrinsic compensation for current-mirror mismatch. - Sizhen Li; Xuecheng Zou; Xiaofei Chen; Zhige Zou; Kai Yu 008; Hao Zhang (APCCAS, 2008)

A 90nm CMOS wide-band voltage-controlled ring oscillator for digital TV-tuner. - Kai Yu 008; Xuecheng Zou; Jianming Lei; Guoyi Yu; Sizhen Li; Yunwu Chen (APCCAS, 2008)

Clock control strategy of four-phase Dickson charge pump for power efficiency improvement. - Kai Yu 008; Xuecheng Zou; Dongsheng Liu; Guoyi Yu; Jianming Lei; Yue Chen (APCCAS, 2008)

Dynamic current limitation circuit for white LED driver. - Xuecheng Zou; Kai Yu 008; Zhaoxia Zheng; Xiaofei Chen; Zhige Zou; Dingbin Liao (APCCAS, 2008)

Dual SPDT/SP3T SOI CMOS switch adopting alternative bias strategy with enhanced performance compared to the conventional case. - Zhi-hao Zhang; Gary Zhang; Kai Yu 008; Jun-ming Lin; Liang Huang; Zu-hua Liu (IEICE Electron. Express, 2016)

Digital Sensorless Current Mode Control Based on Charge Balance Principle and Dual Current Error Compensation for DC-DC Converters in DCM. - Run Min; Qiaoling Tong; Qiao Zhang; Xuecheng Zou; Kai Yu 008; Zhenglin Liu (IEEE Trans. Ind. Electron., 2016)

Design Considerations of Charge Pump for Antenna Switch Controller With SOI CMOS Technology. - Kai Yu 008; Sizhen Li; Gary Zhang; Zhi-hao Zhang; Qiaoling Tong; Xuecheng Zou (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 0.1 to 2.7-GHz SOI SP8T antenna switch adopting body self-adapting bias technique for low-loss high-power applications. - Zhi-hao Zhang; Gary Zhang; Kai Yu 008; Jun-ming Lin; Zu-hua Liu (Int. J. Circuit Theory Appl., 2018)

A compact hybrid envelope tracking supply modulator with wide-band high-slew-rate linear amplifier. - Sizhen Li; Kai Yu 008; Li-xiang Ou; Pan Zhou; Gary Zhang (IEICE Electron. Express, 2020)

A 23-pW NMOS-Only Voltage Reference With Optimum Body Selection for Process Compensation. - Kai Yu 008; Yangrun Zhou; Sizhen Li; Mo Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 0.011%/V LS and -76-dB PSRR Self-Biased CMOS Voltage Reference With Quasi Self-Cascode Current Mirror. - Kai Yu 008; Jiyang Chen; Sizhen Li; Mo Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 521pW, 0.016%/V Line Sensitivity Self-Biased CMOS Voltage Reference With DIBL Effect Compensation Using Adaptive VGS Control. - Kai Yu 008; Shangru Yang; Sizhen Li; Mo Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 140 pW, -77 dB PSRR, PMOS-Only Voltage Reference Using Pre-Regulation Technique With Gate and Bulk Feedback. - Sizhen Li; Yuhao Qiu; Kai Yu 008; Mo Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2025)