A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS. - Amr Elshazly; Ajay Balankutty; Yan-Yu Huang; Kai Yu 016; Frank O'Mahony (VLSIC, 2014)

10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS. - Rajeev K. Dokania; Alexandra M. Kern; Mike He; Adam C. Faust; Richard Tseng; Skyler Weaver; Kai Yu 016; Christiaan Bil; Tao Liang; Frank O'Mahony (ISSCC, 2015)

3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS. - Jihwan Kim; Ajay Balankutty; Amr Elshazly; Yan-Yu Huang; Hang Song; Kai Yu 016; Frank O'Mahony (ISSCC, 2015)

A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS. - Jihwan Kim; Ajay Balankutty; Rajeev K. Dokania; Amr Elshazly; Hyung Seok Kim; Sandipan Kundu; Skyler Weaver; Kai Yu 016; Frank O'Mahony (ISSCC, 2018)

A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET. - Jihwan Kim; Ajay Balankutty; Rajeev K. Dokania; Amr Elshazly; Hyung Seok Kim; Sandipan Kundu; Dan Shi; Skyler Weaver; Kai Yu 016; Frank O'Mahony (IEEE J. Solid State Circuits, 2019)

8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS. - Jihwan Kim; Sandipan Kundu; Ajay Balankutty; Matthew Beach; Bong Chan Kim; Stephen Kim; Yutao Liu; Savyassachi Keshava Murthy; Priya Wali; Kai Yu 016; Hyung Seok Kim; Chuanchang Liu; et al. (ISSCC, 2021)

A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET. - Jihwan Kim; Sandipan Kundu; Ajay Balankutty; Matthew Beach; Bong Chan Kim; Stephen T. Kim; Yutao Liu; Savyasaachi Keshava Murthy; Priya Wali; Kai Yu 016; Hyung Seok Kim; Chuanchang Liu; et al. (IEEE J. Solid State Circuits, 2022)

Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging. - Jihwan Kim; Ariel Cohen 001; Mike Peng Li; Ajay Balankutty; Sandipan Kundu; Ahmad Khairi; Yoel Krupnik; Yoav Segal; Marco Cusmai; Dror Lazar; Ari Gordon; Noam Familia; et al. (CICC, 2024)