A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design. - Li-Rong Wang; Kai-Yu Lo; Shyh-Jye Jou (IEICE Trans. Electron., 2013)

A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques. - Chia-Wen Chang; Kai-Yu Lo; Hossameldin A. Ibrahim; Ming-Chiuan Su; Yuan-Hua Chu; Shyh-Jye Jou (IEICE Trans. Electron., 2016)