Layer assignment for high-performance multi-chip modules. - Kai-Yuan Chao; D. F. Wong 001 (ICCAD, 1994)

Signal integrity optimization on the pad assignment for high-speed VLSI design. - Kai-Yuan Chao; D. F. Wong 001 (ICCAD, 1995)

Thermal placement for high-performance multichip modules. - Kai-Yuan Chao; D. F. Wong 001 (ICCD, 1995)

Floorplanning for Low Power Designs. - Kai-Yuan Chao; D. F. Wong 001 (ISCAS, 1995)

An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. - Shashidhar Thakur; Kai-Yuan Chao; D. F. Wong 001 (ISCAS, 1995)

Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing. - Shashidhar Thakur; Kai-Yuan Chao; D. F. Wong 001 (VLSI Design, 1998)

Flip-Flop and Repeater Insertion for Early Interconnect Planning. - Ruibing Lu; Guoan Zhong; Cheng-Kok Koh; Kai-Yuan Chao (DATE, 2002)

ECO algorithms for removing overlaps between power rails and signal wires. - Hua Xiang 001; Kai-Yuan Chao; D. F. Wong 001 (ICCAD, 2002)

Simultaneous floorplanning and buffer block planning. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jing-Yang Jou; Kai-Yuan Chao (ASP-DAC, 2003)

An ECO algorithm for eliminating crosstalk violations. - Hua Xiang 001; Kai-Yuan Chao; D. F. Wong 001 (ISPD, 2004)

Simultaneous floor plan and buffer-block optimization. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jing-Yang Jou; Kai-Yuan Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. - Hua Xiang 001; Kai-Yuan Chao; Martin D. F. Wong (ISQED, 2005)

Post-routing redundant via insertion and line end extension with via density consideration. - Kuang-Yao Lee; Ting-Chi Wang; Kai-Yuan Chao (ICCAD, 2006)

An ECO routing algorithm for eliminating coupling-capacitance violations. - Hua Xiang 001; Kai-Yuan Chao; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Coupling-aware Dummy Metal Insertion for Lithography. - Liang Deng; Martin D. F. Wong; Kai-Yuan Chao; Hua Xiang 001 (ASP-DAC, 2007)

Is your layout density verification exact?: a fast exact algorithm for density calculation. - Hua Xiang 001; Kai-Yuan Chao; Ruchir Puri; Martin D. F. Wong (ISPD, 2007)

Dummy fill density analysis with coupling constraints. - Hua Xiang 001; Liang Deng; Ruchir Puri; Kai-Yuan Chao; Martin D. F. Wong (ISPD, 2007)

Optimal post-routing redundant via insertion. - Kuang-Yao Lee; Cheng-Kok Koh; Ting-Chi Wang; Kai-Yuan Chao (ISPD, 2008)

Fast and Optimal Redundant Via Insertion. - Kuang-Yao Lee; Cheng-Kok Koh; Ting-Chi Wang; Kai-Yuan Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. - Hua Xiang 001; Kai-Yuan Chao; Ruchir Puri; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Fast Dummy-Fill Density Analysis With Coupling Constraints. - Hua Xiang 001; Liang Deng; Ruchir Puri; Kai-Yuan Chao; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Spare-cell-aware multilevel analytical placement. - Zhe-Wei Jiang; Meng-Kai Hsu; Yao-Wen Chang; Kai-Yuan Chao (DAC, 2009)

Wire shaping is practical. - Hongbo Zhang 001; Martin D. F. Wong; Kai-Yuan Chao; Liang Deng (ISPD, 2009)

Configurable multi-product floorplanning. - Qiang Ma 002; Martin D. F. Wong; Kai-Yuan Chao (ASP-DAC, 2010)

On process-aware 1-D standard cell design. - Hongbo Zhang 001; Martin D. F. Wong; Kai-Yuan Chao (ASP-DAC, 2010)

Multi-threaded collision-aware global routing with bounded-length maze routing. - Wen-Hao Liu 001; Wei-Chun Kao; Yih-Lang Li; Kai-Yuan Chao (DAC, 2010)

Optimal Double Via Insertion With On-Track Preference. - Kuang-Yao Lee; Ting-Chi Wang; Cheng-Kok Koh; Kai-Yuan Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Simultaneous redundant via insertion and line end extension for yield optimization. - Shing-Tung Lin; Kuang-Yao Lee; Ting-Chi Wang; Cheng-Kok Koh; Kai-Yuan Chao (ASP-DAC, 2011)

Mask cost reduction with circuit performance consideration for self-aligned double patterning. - Hongbo Zhang 001; Yuelin Du; Martin D. F. Wong; Kai-Yuan Chao (ASP-DAC, 2011)

High-quality global routing for multiple dynamic supply voltage designs. - Wen-Hao Liu 001; Yih-Lang Li; Kai-Yuan Chao (ICCAD, 2011)

Lithography-aware layout modification considering performance impact. - Hongbo Zhang 001; Yuelin Du; Martin D. F. Wong; Kai-Yuan Chao (ISQED, 2011)

Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design. - Yuelin Du; Hongbo Zhang 001; Martin D. F. Wong; Kai-Yuan Chao (ASP-DAC, 2012)

Scaling the "Memory Wall": Designer track. - Shih-Lien Lu; Tanay Karnik; Ganapati Srinivasa; Kai-Yuan Chao; Doug Carmean; Jim Held (ICCAD, 2012)

A Practical Low-Power Nonregular Interconnect Design With Manufacturing for Design Approach. - Hongbo Zhang 001; Martin D. F. Wong; Kai-Yuan Chao; Liang Deng (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Symmetrical buffered clock-tree synthesis with supply-voltage alignment. - Xin-Wei Shih; Tzu-Hsuan Hsu; Hsu-Chieh Lee; Yao-Wen Chang; Kai-Yuan Chao (ASP-DAC, 2013)

NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing. - Wen-Hao Liu 001; Wei-Chun Kao; Yih-Lang Li; Kai-Yuan Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

A study on the use of parallel wiring techniques for sub-20nm designs. - Rickard Ewetz; Wen-Hao Liu 001; Kai-Yuan Chao; Ting-Chi Wang; Cheng-Kok Koh (ACM Great Lakes Symposium on VLSI, 2014)

Delay-driven layer assignment for advanced technology nodes. - Szu-Yuan Han; Wen-Hao Liu 001; Rickard Ewetz; Cheng-Kok Koh; Kai-Yuan Chao; Ting-Chi Wang (ASP-DAC, 2017)

Multi-Package Co-Design for Chiplet Integration. - Zhen Zhuang; Bei Yu 001; Kai-Yuan Chao; Tsung-Yi Ho (ICCAD, 2022)

Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars. - Genggeng Liu; Xinghai Zhang; Wenzhong Guo; Xing Huang 001; Wen-Hao Liu 001; Kai-Yuan Chao; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding. - Zhen Zhuang; Kai-Yuan Chao; Bei Yu 001; Tsung-Yi Ho; Martin D. F. Wong (ICCAD, 2023)

Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs. - Yuan Pu 001; Fangzhou Liu; Yu Zhang 189; Zhuolun He; Yibo Lin; Kai-Yuan Chao; Bei Yu 001 (DAC, 2024)

Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells. - Yu Zhang 189; Yuan Pu 001; Fangzhou Liu; Peiyu Liao; Kai-Yuan Chao; Keren Zhu 001; Yibo Lin; Bei Yu 001 (ISPD, 2024)