Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs. - Kai Zhang 023; Shuming Chen; Sheng Liu 001; Yaohua Wang; Junhui Huang (ASICON, 2011)

AIFSP: An Adaptive Instruction Flow Stream Processor. - Yaohua Wang; Shuming Chen; Jianghua Wan; Kai Zhang 023; Shenggang Chen (ISVLSI, 2011)

SUCA: a scalable unicore architecture with novel instruction encoding and distributed execution control. - Hu Chen; Shuming Chen; Yaohua Wang; Kai Zhang 023 (IEICE Electron. Express, 2011)

LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs. - Sheng Liu 001; Shuming Chen; Xi Ning; Jianghua Wan; Hu Chen; Kai Zhang 023; Yaohua Wang (IEICE Electron. Express, 2011)

Architectural Implications for SIMD Processors in the Wireless Communication Domain. - Yaohua Wang; Kai Zhang 023; Jianghua Wan; Sheng Liu 001; Xi Ning; Shuming Chen (HPCC-ICESS, 2012)

Architecture Design Trade-offs among VLIW SIMD and Multi-core Schemes. - Yaohua Wang; Shuming Chen; Kai Zhang 023; Hu Chen; Xiaowen Chen (IPDPS Workshops, 2012)

Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures. - Yaohua Wang; Shuming Chen; Kai Zhang 023; Jianghua Wan; Xiaowen Chen; Hu Chen; Haibo Wang 004 (IEEE Comput. Archit. Lett., 2012)

A cost conscious performance model for media processors. - Yaohua Wang; Shuming Chen; Kai Zhang 023; Jianghua Wan; Hu Chen; Sheng Liu 001; Xi Ning (IEICE Electron. Express, 2012)

CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors. - Kai Zhang 023; Shuming Chen; Hu Chen; Yaohua Wang; Xiaowen Chen; Sheng Liu 001; Wei Liu 013 (IEICE Electron. Express, 2012)

A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments. - Yaohua Wang; Shuming Chen; Jianghua Wan; Jiayuan Meng; Kai Zhang 023; Wei Liu 013; Xi Ning (HPCA, 2013)

Redefining the relationship between scalar and parallel units in SIMD architectures. - Yaohua Wang; Shuming Chen; Jianghua Wan; Kai Zhang 023 (ISCAS, 2013)

A Fine-Grained Pipelined Implementation of LU Decomposition on SIMD Processors. - Kai Zhang 023; Shuming Chen; Wei Liu 013; Xi Ning (NPC, 2013)

A novel QPP interleaver for parallel turbo decoder. - Wei Liu 013; Shuming Chen; Hu Chen; Yaohua Wang; Sheng Liu 001; Kai Zhang 023; Xi Ning (IEICE Electron. Express, 2013)

Breaking the performance bottleneck of sparse matrix-vector multiplication on SIMD processors. - Kai Zhang 023; Shuming Chen; Yaohua Wang; Jianghua Wan (IEICE Electron. Express, 2013)

Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures. - Yaohua Wang; Shuming Chen; Hu Chen; Jianghua Wan; Kai Zhang 023; Sheng Liu 001 (IEICE Trans. Inf. Syst., 2013)

FT-Matrix: A Coordination-Aware Architecture for Signal Processing. - Shuming Chen; Yaohua Wang; Sheng Liu 001; Jianghua Wan; Haiyan Chen; Hengzhu Liu; Kai Zhang 023; Xiangyuan Liu; Xi Ning (IEEE Micro, 2014)