On channel segmentation design for row-based FPGAs. - Kai Zhu 001; D. F. Wong 001 (ICCAD, 1992)

Fast Boolean matching for field-programmable gate arrays. - Kai Zhu 001; D. F. Wong 001 (EURO-DAC, 1993)

Switch module design with application to two-dimensional segmentation design. - Kai Zhu 001; D. F. Wong 001; Yao-Wen Chang (ICCAD, 1993)

Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs. - Kai Zhu 001; D. F. Wong 001 (DAC, 1994)

A new global routing algorithm for FPGAs. - Yao-Wen Chang; Shashidhar Thakur; Kai Zhu 001; D. F. Wong 001 (ICCAD, 1994)

Clock skew minimization during FPGA placement. - Kai Zhu 001; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Circuit Partitioning with Complex Resource Constraints in FPGAs. - Huiqun Liu; Kai Zhu 001; D. F. Wong 001 (FPGA, 1998)

Switch bound allocation for maximizing routability in timing-driven routing of FPGA's. - Kai Zhu 001; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Timing-driven routing for symmetrical array-based FPGAs. - Yao-Wen Chang; Kai Zhu 001; D. F. Wong 001 (ACM Trans. Design Autom. Electr. Syst., 2000)

FPGA Partitioning with Complex Resource Constraints. - Huiqun Liu; Kai Zhu 001; D. F. Wong 001 (VLSI Design, 2000)

Analysis of FPGA/FPIC switch modules. - Yao-Wen Chang; Kai Zhu 001; Guang-Ming Wu; D. F. Wong 001; C. K. Wong (ACM Trans. Design Autom. Electr. Syst., 2003)

Post-route LUT output polarity selection for timing optimization. - Kai Zhu 001 (FPGA, 2007)