A scalable and fault-tolerant routing algorithm for NoCs. - Zewen Shi; Kaidi You; Yan Ying; Bei Huang; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2010)

A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost. - Yan Ying; Kaidi You; Liyang Zhou; Heng Quan; Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng (ISCAS, 2012)

An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. - Zhiyi Yu; Kaidi You; Ruijin Xiao; Heng Quan; Peng Ou; Yan Ying; Haofan Yang 001; Ming-e Jing; Xiaoyang Zeng (ISSCC, 2012)

A Fully Programmable Reed-Solomon Decoder on a Multi-Core Processor Platform. - Bei Huang; Kaidi You; Yun Chen 001; Zhiyi Yu; Xiaoyang Zeng (IEICE Trans. Inf. Syst., 2012)

A 16-Core Processor With Shared-Memory and Message-Passing Communications. - Zhiyi Yu; Ruijin Xiao; Kaidi You; Heng Quan; Peng Ou; Zheng Yu 001; Maofei He; Jiajie Zhang; Yan Ying; Haofan Yang 001; Jun Han 003; Xu Cheng 002; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)