Towards Developing High Performance RISC-V Processors Using Agile Methodology. - Yinan Xu 001; Zihao Yu; Dan Tang; Guokai Chen; Lu Chen; Lingrui Gou; Yue Jin; Qianruo Li; Xin Li; Zuojun Li; Jiawei Lin; Tong Liu; et al. (MICRO, 2022)

Model Checking TileLink Cache Coherence Protocols By Murphi. - Zimin Li; Yongjian Li; Kaifan Wang; Kun Ma; Shizhen Yu (ICCD, 2023)

Functional Verification for Agile Processor Development: A Case for Workflow Integration. - Yinan Xu 001; Zihao Yu; Kaifan Wang; Huaqiang Wang; Jiawei Lin; Yue Jin; Linjuan Zhang; Zifei Zhang 001; Dan Tang; Sa Wang; Kan Shi; Ninghui Sun; et al. (J. Comput. Sci. Technol., 2023)

XiangShan: An Open-Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards. - Kaifan Wang; Jian Chen; Yinan Xu 001; Zihao Yu; Zifei Zhang 001; Guokai Chen; Xuan Hu; Linjuan Zhang; Xi Chen; Wei He; Dan Tang; Ninghui Sun; et al. (HCS, 2024)

OEHR: An Orthopedic Electronic Health Record Dataset. - Yibo Xie; Kaifan Wang; Jiawei Zheng; Feiyan Liu; Xiaoli Wang 002; Guofeng Huang (SIGIR, 2024)

XiangShan: An Open Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards. - Kaifan Wang; Jian Chen; Yinan Xu 001; Zihao Yu; Wei He; Dan Tang; Ninghui Sun; Yungang Bao (IEEE Micro, 2025)